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Canonicalize access to function attributes to use the simpler API. getAttributes().getAttribute(AttributeSet::FunctionIndex, Kind) => getFnAttribute(Kind) getAttributes().hasAttribute(AttributeSet::FunctionIndex, Kind) => hasFnAttribute(Kind) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229218 91177308-0d34-0410-b5e6-96231b3b80d8
918 lines
31 KiB
C++
918 lines
31 KiB
C++
//===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64ConditionalCompares pass which reduces
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// branching and code size by using the conditional compare instructions CCMP,
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// CCMN, and FCMP.
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//
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// The CFG transformations for forming conditional compares are very similar to
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// if-conversion, and this pass should run immediately before the early
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// if-conversion pass.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineTraceMetrics.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-ccmp"
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// Absolute maximum number of instructions allowed per speculated block.
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// This bypasses all other heuristics, so it should be set fairly high.
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static cl::opt<unsigned> BlockInstrLimit(
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"aarch64-ccmp-limit", cl::init(30), cl::Hidden,
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cl::desc("Maximum number of instructions per speculated block."));
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// Stress testing mode - disable heuristics.
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static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
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cl::desc("Turn all knobs to 11"));
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STATISTIC(NumConsidered, "Number of ccmps considered");
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STATISTIC(NumPhiRejs, "Number of ccmps rejected (PHI)");
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STATISTIC(NumPhysRejs, "Number of ccmps rejected (Physregs)");
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STATISTIC(NumPhi2Rejs, "Number of ccmps rejected (PHI2)");
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STATISTIC(NumHeadBranchRejs, "Number of ccmps rejected (Head branch)");
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STATISTIC(NumCmpBranchRejs, "Number of ccmps rejected (CmpBB branch)");
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STATISTIC(NumCmpTermRejs, "Number of ccmps rejected (CmpBB is cbz...)");
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STATISTIC(NumImmRangeRejs, "Number of ccmps rejected (Imm out of range)");
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STATISTIC(NumLiveDstRejs, "Number of ccmps rejected (Cmp dest live)");
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STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
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STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
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STATISTIC(NumSpeculateRejs, "Number of ccmps rejected (Can't speculate)");
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STATISTIC(NumConverted, "Number of ccmp instructions created");
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STATISTIC(NumCompBranches, "Number of cbz/cbnz branches converted");
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//===----------------------------------------------------------------------===//
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// SSACCmpConv
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//===----------------------------------------------------------------------===//
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//
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// The SSACCmpConv class performs ccmp-conversion on SSA form machine code
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// after determining if it is possible. The class contains no heuristics;
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// external code should be used to determine when ccmp-conversion is a good
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// idea.
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//
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// CCmp-formation works on a CFG representing chained conditions, typically
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// from C's short-circuit || and && operators:
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//
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// From: Head To: Head
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// / | CmpBB
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// / | / |
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// | CmpBB / |
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// | / | Tail |
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// | / | | |
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// Tail | | |
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// | | | |
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// ... ... ... ...
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//
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// The Head block is terminated by a br.cond instruction, and the CmpBB block
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// contains compare + br.cond. Tail must be a successor of both.
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//
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// The cmp-conversion turns the compare instruction in CmpBB into a conditional
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// compare, and merges CmpBB into Head, speculatively executing its
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// instructions. The AArch64 conditional compare instructions have an immediate
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// operand that specifies the NZCV flag values when the condition is false and
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// the compare isn't executed. This makes it possible to chain compares with
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// different condition codes.
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//
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// Example:
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//
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// if (a == 5 || b == 17)
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// foo();
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//
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// Head:
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// cmp w0, #5
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// b.eq Tail
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// CmpBB:
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// cmp w1, #17
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// b.eq Tail
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// ...
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// Tail:
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// bl _foo
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//
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// Becomes:
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//
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// Head:
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// cmp w0, #5
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// ccmp w1, #17, 4, ne ; 4 = nZcv
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// b.eq Tail
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// ...
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// Tail:
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// bl _foo
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//
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// The ccmp condition code is the one that would cause the Head terminator to
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// branch to CmpBB.
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//
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// FIXME: It should also be possible to speculate a block on the critical edge
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// between Head and Tail, just like if-converting a diamond.
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//
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// FIXME: Handle PHIs in Tail by turning them into selects (if-conversion).
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namespace {
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class SSACCmpConv {
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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public:
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/// The first block containing a conditional branch, dominating everything
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/// else.
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MachineBasicBlock *Head;
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/// The block containing cmp+br.cond with a successor shared with Head.
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MachineBasicBlock *CmpBB;
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/// The common successor for Head and CmpBB.
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MachineBasicBlock *Tail;
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/// The compare instruction in CmpBB that can be converted to a ccmp.
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MachineInstr *CmpMI;
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private:
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/// The branch condition in Head as determined by AnalyzeBranch.
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SmallVector<MachineOperand, 4> HeadCond;
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/// The condition code that makes Head branch to CmpBB.
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AArch64CC::CondCode HeadCmpBBCC;
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/// The branch condition in CmpBB.
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SmallVector<MachineOperand, 4> CmpBBCond;
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/// The condition code that makes CmpBB branch to Tail.
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AArch64CC::CondCode CmpBBTailCC;
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/// Check if the Tail PHIs are trivially convertible.
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bool trivialTailPHIs();
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/// Remove CmpBB from the Tail PHIs.
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void updateTailPHIs();
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/// Check if an operand defining DstReg is dead.
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bool isDeadDef(unsigned DstReg);
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/// Find the compare instruction in MBB that controls the conditional branch.
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/// Return NULL if a convertible instruction can't be found.
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MachineInstr *findConvertibleCompare(MachineBasicBlock *MBB);
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/// Return true if all non-terminator instructions in MBB can be safely
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/// speculated.
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bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
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public:
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/// runOnMachineFunction - Initialize per-function data structures.
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void runOnMachineFunction(MachineFunction &MF) {
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this->MF = &MF;
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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}
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/// If the sub-CFG headed by MBB can be cmp-converted, initialize the
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/// internal state, and return true.
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bool canConvert(MachineBasicBlock *MBB);
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/// Cmo-convert the last block passed to canConvertCmp(), assuming
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/// it is possible. Add any erased blocks to RemovedBlocks.
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void convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks);
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/// Return the expected code size delta if the conversion into a
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/// conditional compare is performed.
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int expectedCodeSizeDelta() const;
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};
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} // end anonymous namespace
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// Check that all PHIs in Tail are selecting the same value from Head and CmpBB.
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// This means that no if-conversion is required when merging CmpBB into Head.
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bool SSACCmpConv::trivialTailPHIs() {
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for (auto &I : *Tail) {
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if (!I.isPHI())
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break;
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unsigned HeadReg = 0, CmpBBReg = 0;
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// PHI operands come in (VReg, MBB) pairs.
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for (unsigned oi = 1, oe = I.getNumOperands(); oi != oe; oi += 2) {
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MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB();
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unsigned Reg = I.getOperand(oi).getReg();
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if (MBB == Head) {
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assert((!HeadReg || HeadReg == Reg) && "Inconsistent PHI operands");
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HeadReg = Reg;
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}
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if (MBB == CmpBB) {
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assert((!CmpBBReg || CmpBBReg == Reg) && "Inconsistent PHI operands");
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CmpBBReg = Reg;
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}
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}
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if (HeadReg != CmpBBReg)
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return false;
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}
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return true;
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}
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// Assuming that trivialTailPHIs() is true, update the Tail PHIs by simply
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// removing the CmpBB operands. The Head operands will be identical.
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void SSACCmpConv::updateTailPHIs() {
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for (auto &I : *Tail) {
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if (!I.isPHI())
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break;
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// I is a PHI. It can have multiple entries for CmpBB.
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for (unsigned oi = I.getNumOperands(); oi > 2; oi -= 2) {
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// PHI operands are (Reg, MBB) at (oi-2, oi-1).
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if (I.getOperand(oi - 1).getMBB() == CmpBB) {
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I.RemoveOperand(oi - 1);
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I.RemoveOperand(oi - 2);
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}
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}
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}
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}
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// This pass runs before the AArch64DeadRegisterDefinitions pass, so compares
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// are still writing virtual registers without any uses.
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bool SSACCmpConv::isDeadDef(unsigned DstReg) {
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// Writes to the zero register are dead.
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if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
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return true;
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if (!TargetRegisterInfo::isVirtualRegister(DstReg))
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return false;
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// A virtual register def without any uses will be marked dead later, and
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// eventually replaced by the zero register.
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return MRI->use_nodbg_empty(DstReg);
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}
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// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
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// corresponding to TBB.
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// Return
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static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
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// A normal br.cond simply has the condition code.
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if (Cond[0].getImm() != -1) {
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assert(Cond.size() == 1 && "Unknown Cond array format");
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CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
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return true;
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}
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// For tbz and cbz instruction, the opcode is next.
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switch (Cond[1].getImm()) {
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default:
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// This includes tbz / tbnz branches which can't be converted to
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// ccmp + br.cond.
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return false;
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case AArch64::CBZW:
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case AArch64::CBZX:
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assert(Cond.size() == 3 && "Unknown Cond array format");
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CC = AArch64CC::EQ;
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return true;
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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assert(Cond.size() == 3 && "Unknown Cond array format");
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CC = AArch64CC::NE;
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return true;
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}
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}
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MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
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MachineBasicBlock::iterator I = MBB->getFirstTerminator();
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if (I == MBB->end())
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return nullptr;
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// The terminator must be controlled by the flags.
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if (!I->readsRegister(AArch64::NZCV)) {
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switch (I->getOpcode()) {
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case AArch64::CBZW:
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case AArch64::CBZX:
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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// These can be converted into a ccmp against #0.
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return I;
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}
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++NumCmpTermRejs;
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DEBUG(dbgs() << "Flags not used by terminator: " << *I);
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return nullptr;
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}
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// Now find the instruction controlling the terminator.
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for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {
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--I;
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assert(!I->isTerminator() && "Spurious terminator");
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switch (I->getOpcode()) {
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// cmp is an alias for subs with a dead destination register.
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case AArch64::SUBSWri:
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case AArch64::SUBSXri:
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// cmn is an alias for adds with a dead destination register.
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case AArch64::ADDSWri:
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case AArch64::ADDSXri:
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// Check that the immediate operand is within range, ccmp wants a uimm5.
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// Rd = SUBSri Rn, imm, shift
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if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
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DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I);
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++NumImmRangeRejs;
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return nullptr;
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}
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// Fall through.
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case AArch64::SUBSWrr:
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case AArch64::SUBSXrr:
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case AArch64::ADDSWrr:
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case AArch64::ADDSXrr:
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if (isDeadDef(I->getOperand(0).getReg()))
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return I;
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DEBUG(dbgs() << "Can't convert compare with live destination: " << *I);
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++NumLiveDstRejs;
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return nullptr;
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case AArch64::FCMPSrr:
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case AArch64::FCMPDrr:
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case AArch64::FCMPESrr:
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case AArch64::FCMPEDrr:
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return I;
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}
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// Check for flag reads and clobbers.
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MIOperands::PhysRegInfo PRI =
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MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI);
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if (PRI.Reads) {
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// The ccmp doesn't produce exactly the same flags as the original
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// compare, so reject the transform if there are uses of the flags
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// besides the terminators.
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DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I);
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++NumMultNZCVUses;
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return nullptr;
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}
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if (PRI.Clobbers) {
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DEBUG(dbgs() << "Not convertible compare: " << *I);
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++NumUnknNZCVDefs;
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return nullptr;
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}
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}
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DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
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return nullptr;
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}
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/// Determine if all the instructions in MBB can safely
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/// be speculated. The terminators are not considered.
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///
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/// Only CmpMI is allowed to clobber the flags.
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///
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bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
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const MachineInstr *CmpMI) {
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// Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
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// get right.
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if (!MBB->livein_empty()) {
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DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
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return false;
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}
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unsigned InstrCount = 0;
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// Check all instructions, except the terminators. It is assumed that
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// terminators never have side effects or define any used register values.
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for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {
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if (I.isDebugValue())
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continue;
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if (++InstrCount > BlockInstrLimit && !Stress) {
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DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
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<< BlockInstrLimit << " instructions.\n");
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return false;
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}
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// There shouldn't normally be any phis in a single-predecessor block.
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if (I.isPHI()) {
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DEBUG(dbgs() << "Can't hoist: " << I);
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return false;
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}
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// Don't speculate loads. Note that it may be possible and desirable to
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// speculate GOT or constant pool loads that are guaranteed not to trap,
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// but we don't support that for now.
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if (I.mayLoad()) {
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DEBUG(dbgs() << "Won't speculate load: " << I);
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return false;
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}
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// We never speculate stores, so an AA pointer isn't necessary.
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bool DontMoveAcrossStore = true;
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if (!I.isSafeToMove(TII, nullptr, DontMoveAcrossStore)) {
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DEBUG(dbgs() << "Can't speculate: " << I);
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return false;
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}
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// Only CmpMI is allowed to clobber the flags.
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if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
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DEBUG(dbgs() << "Clobbers flags: " << I);
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return false;
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}
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}
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return true;
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}
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/// Analyze the sub-cfg rooted in MBB, and return true if it is a potential
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/// candidate for cmp-conversion. Fill out the internal state.
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///
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bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
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Head = MBB;
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Tail = CmpBB = nullptr;
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if (Head->succ_size() != 2)
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return false;
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MachineBasicBlock *Succ0 = Head->succ_begin()[0];
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MachineBasicBlock *Succ1 = Head->succ_begin()[1];
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// CmpBB can only have a single predecessor. Tail is allowed many.
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if (Succ0->pred_size() != 1)
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std::swap(Succ0, Succ1);
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// Succ0 is our candidate for CmpBB.
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if (Succ0->pred_size() != 1 || Succ0->succ_size() != 2)
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return false;
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CmpBB = Succ0;
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Tail = Succ1;
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if (!CmpBB->isSuccessor(Tail))
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return false;
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// The CFG topology checks out.
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DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber() << " -> BB#"
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<< CmpBB->getNumber() << " -> BB#" << Tail->getNumber() << '\n');
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++NumConsidered;
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// Tail is allowed to have many predecessors, but we can't handle PHIs yet.
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//
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// FIXME: Real PHIs could be if-converted as long as the CmpBB values are
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// defined before The CmpBB cmp clobbers the flags. Alternatively, it should
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// always be safe to sink the ccmp down to immediately before the CmpBB
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// terminators.
|
|
if (!trivialTailPHIs()) {
|
|
DEBUG(dbgs() << "Can't handle phis in Tail.\n");
|
|
++NumPhiRejs;
|
|
return false;
|
|
}
|
|
|
|
if (!Tail->livein_empty()) {
|
|
DEBUG(dbgs() << "Can't handle live-in physregs in Tail.\n");
|
|
++NumPhysRejs;
|
|
return false;
|
|
}
|
|
|
|
// CmpBB should never have PHIs since Head is its only predecessor.
|
|
// FIXME: Clean them up if it happens.
|
|
if (!CmpBB->empty() && CmpBB->front().isPHI()) {
|
|
DEBUG(dbgs() << "Can't handle phis in CmpBB.\n");
|
|
++NumPhi2Rejs;
|
|
return false;
|
|
}
|
|
|
|
if (!CmpBB->livein_empty()) {
|
|
DEBUG(dbgs() << "Can't handle live-in physregs in CmpBB.\n");
|
|
++NumPhysRejs;
|
|
return false;
|
|
}
|
|
|
|
// The branch we're looking to eliminate must be analyzable.
|
|
HeadCond.clear();
|
|
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
|
|
if (TII->AnalyzeBranch(*Head, TBB, FBB, HeadCond)) {
|
|
DEBUG(dbgs() << "Head branch not analyzable.\n");
|
|
++NumHeadBranchRejs;
|
|
return false;
|
|
}
|
|
|
|
// This is weird, probably some sort of degenerate CFG, or an edge to a
|
|
// landing pad.
|
|
if (!TBB || HeadCond.empty()) {
|
|
DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n");
|
|
++NumHeadBranchRejs;
|
|
return false;
|
|
}
|
|
|
|
if (!parseCond(HeadCond, HeadCmpBBCC)) {
|
|
DEBUG(dbgs() << "Unsupported branch type on Head\n");
|
|
++NumHeadBranchRejs;
|
|
return false;
|
|
}
|
|
|
|
// Make sure the branch direction is right.
|
|
if (TBB != CmpBB) {
|
|
assert(TBB == Tail && "Unexpected TBB");
|
|
HeadCmpBBCC = AArch64CC::getInvertedCondCode(HeadCmpBBCC);
|
|
}
|
|
|
|
CmpBBCond.clear();
|
|
TBB = FBB = nullptr;
|
|
if (TII->AnalyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
|
|
DEBUG(dbgs() << "CmpBB branch not analyzable.\n");
|
|
++NumCmpBranchRejs;
|
|
return false;
|
|
}
|
|
|
|
if (!TBB || CmpBBCond.empty()) {
|
|
DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n");
|
|
++NumCmpBranchRejs;
|
|
return false;
|
|
}
|
|
|
|
if (!parseCond(CmpBBCond, CmpBBTailCC)) {
|
|
DEBUG(dbgs() << "Unsupported branch type on CmpBB\n");
|
|
++NumCmpBranchRejs;
|
|
return false;
|
|
}
|
|
|
|
if (TBB != Tail)
|
|
CmpBBTailCC = AArch64CC::getInvertedCondCode(CmpBBTailCC);
|
|
|
|
DEBUG(dbgs() << "Head->CmpBB on " << AArch64CC::getCondCodeName(HeadCmpBBCC)
|
|
<< ", CmpBB->Tail on " << AArch64CC::getCondCodeName(CmpBBTailCC)
|
|
<< '\n');
|
|
|
|
CmpMI = findConvertibleCompare(CmpBB);
|
|
if (!CmpMI)
|
|
return false;
|
|
|
|
if (!canSpeculateInstrs(CmpBB, CmpMI)) {
|
|
++NumSpeculateRejs;
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
|
|
DEBUG(dbgs() << "Merging BB#" << CmpBB->getNumber() << " into BB#"
|
|
<< Head->getNumber() << ":\n" << *CmpBB);
|
|
|
|
// All CmpBB instructions are moved into Head, and CmpBB is deleted.
|
|
// Update the CFG first.
|
|
updateTailPHIs();
|
|
Head->removeSuccessor(CmpBB);
|
|
CmpBB->removeSuccessor(Tail);
|
|
Head->transferSuccessorsAndUpdatePHIs(CmpBB);
|
|
DebugLoc TermDL = Head->getFirstTerminator()->getDebugLoc();
|
|
TII->RemoveBranch(*Head);
|
|
|
|
// If the Head terminator was one of the cbz / tbz branches with built-in
|
|
// compare, we need to insert an explicit compare instruction in its place.
|
|
if (HeadCond[0].getImm() == -1) {
|
|
++NumCompBranches;
|
|
unsigned Opc = 0;
|
|
switch (HeadCond[1].getImm()) {
|
|
case AArch64::CBZW:
|
|
case AArch64::CBNZW:
|
|
Opc = AArch64::SUBSWri;
|
|
break;
|
|
case AArch64::CBZX:
|
|
case AArch64::CBNZX:
|
|
Opc = AArch64::SUBSXri;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Cannot convert Head branch");
|
|
}
|
|
const MCInstrDesc &MCID = TII->get(Opc);
|
|
// Create a dummy virtual register for the SUBS def.
|
|
unsigned DestReg =
|
|
MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
|
|
// Insert a SUBS Rn, #0 instruction instead of the cbz / cbnz.
|
|
BuildMI(*Head, Head->end(), TermDL, MCID)
|
|
.addReg(DestReg, RegState::Define | RegState::Dead)
|
|
.addOperand(HeadCond[2])
|
|
.addImm(0)
|
|
.addImm(0);
|
|
// SUBS uses the GPR*sp register classes.
|
|
MRI->constrainRegClass(HeadCond[2].getReg(),
|
|
TII->getRegClass(MCID, 1, TRI, *MF));
|
|
}
|
|
|
|
Head->splice(Head->end(), CmpBB, CmpBB->begin(), CmpBB->end());
|
|
|
|
// Now replace CmpMI with a ccmp instruction that also considers the incoming
|
|
// flags.
|
|
unsigned Opc = 0;
|
|
unsigned FirstOp = 1; // First CmpMI operand to copy.
|
|
bool isZBranch = false; // CmpMI is a cbz/cbnz instruction.
|
|
switch (CmpMI->getOpcode()) {
|
|
default:
|
|
llvm_unreachable("Unknown compare opcode");
|
|
case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break;
|
|
case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break;
|
|
case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break;
|
|
case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break;
|
|
case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break;
|
|
case AArch64::ADDSWrr: Opc = AArch64::CCMNWr; break;
|
|
case AArch64::ADDSXri: Opc = AArch64::CCMNXi; break;
|
|
case AArch64::ADDSXrr: Opc = AArch64::CCMNXr; break;
|
|
case AArch64::FCMPSrr: Opc = AArch64::FCCMPSrr; FirstOp = 0; break;
|
|
case AArch64::FCMPDrr: Opc = AArch64::FCCMPDrr; FirstOp = 0; break;
|
|
case AArch64::FCMPESrr: Opc = AArch64::FCCMPESrr; FirstOp = 0; break;
|
|
case AArch64::FCMPEDrr: Opc = AArch64::FCCMPEDrr; FirstOp = 0; break;
|
|
case AArch64::CBZW:
|
|
case AArch64::CBNZW:
|
|
Opc = AArch64::CCMPWi;
|
|
FirstOp = 0;
|
|
isZBranch = true;
|
|
break;
|
|
case AArch64::CBZX:
|
|
case AArch64::CBNZX:
|
|
Opc = AArch64::CCMPXi;
|
|
FirstOp = 0;
|
|
isZBranch = true;
|
|
break;
|
|
}
|
|
|
|
// The ccmp instruction should set the flags according to the comparison when
|
|
// Head would have branched to CmpBB.
|
|
// The NZCV immediate operand should provide flags for the case where Head
|
|
// would have branched to Tail. These flags should cause the new Head
|
|
// terminator to branch to tail.
|
|
unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC);
|
|
const MCInstrDesc &MCID = TII->get(Opc);
|
|
MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
|
|
TII->getRegClass(MCID, 0, TRI, *MF));
|
|
if (CmpMI->getOperand(FirstOp + 1).isReg())
|
|
MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
|
|
TII->getRegClass(MCID, 1, TRI, *MF));
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
|
|
.addOperand(CmpMI->getOperand(FirstOp)); // Register Rn
|
|
if (isZBranch)
|
|
MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
|
|
else
|
|
MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
|
|
MIB.addImm(NZCV).addImm(HeadCmpBBCC);
|
|
|
|
// If CmpMI was a terminator, we need a new conditional branch to replace it.
|
|
// This now becomes a Head terminator.
|
|
if (isZBranch) {
|
|
bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||
|
|
CmpMI->getOpcode() == AArch64::CBNZX;
|
|
BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
|
|
.addImm(isNZ ? AArch64CC::NE : AArch64CC::EQ)
|
|
.addOperand(CmpMI->getOperand(1)); // Branch target.
|
|
}
|
|
CmpMI->eraseFromParent();
|
|
Head->updateTerminator();
|
|
|
|
RemovedBlocks.push_back(CmpBB);
|
|
CmpBB->eraseFromParent();
|
|
DEBUG(dbgs() << "Result:\n" << *Head);
|
|
++NumConverted;
|
|
}
|
|
|
|
int SSACCmpConv::expectedCodeSizeDelta() const {
|
|
int delta = 0;
|
|
// If the Head terminator was one of the cbz / tbz branches with built-in
|
|
// compare, we need to insert an explicit compare instruction in its place
|
|
// plus a branch instruction.
|
|
if (HeadCond[0].getImm() == -1) {
|
|
switch (HeadCond[1].getImm()) {
|
|
case AArch64::CBZW:
|
|
case AArch64::CBNZW:
|
|
case AArch64::CBZX:
|
|
case AArch64::CBNZX:
|
|
// Therefore delta += 1
|
|
delta = 1;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Cannot convert Head branch");
|
|
}
|
|
}
|
|
// If the Cmp terminator was one of the cbz / tbz branches with
|
|
// built-in compare, it will be turned into a compare instruction
|
|
// into Head, but we do not save any instruction.
|
|
// Otherwise, we save the branch instruction.
|
|
switch (CmpMI->getOpcode()) {
|
|
default:
|
|
--delta;
|
|
break;
|
|
case AArch64::CBZW:
|
|
case AArch64::CBNZW:
|
|
case AArch64::CBZX:
|
|
case AArch64::CBNZX:
|
|
break;
|
|
}
|
|
return delta;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// AArch64ConditionalCompares Pass
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
namespace {
|
|
class AArch64ConditionalCompares : public MachineFunctionPass {
|
|
const TargetInstrInfo *TII;
|
|
const TargetRegisterInfo *TRI;
|
|
MCSchedModel SchedModel;
|
|
// Does the proceeded function has Oz attribute.
|
|
bool MinSize;
|
|
MachineRegisterInfo *MRI;
|
|
MachineDominatorTree *DomTree;
|
|
MachineLoopInfo *Loops;
|
|
MachineTraceMetrics *Traces;
|
|
MachineTraceMetrics::Ensemble *MinInstr;
|
|
SSACCmpConv CmpConv;
|
|
|
|
public:
|
|
static char ID;
|
|
AArch64ConditionalCompares() : MachineFunctionPass(ID) {}
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override;
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
|
const char *getPassName() const override {
|
|
return "AArch64 Conditional Compares";
|
|
}
|
|
|
|
private:
|
|
bool tryConvert(MachineBasicBlock *);
|
|
void updateDomTree(ArrayRef<MachineBasicBlock *> Removed);
|
|
void updateLoops(ArrayRef<MachineBasicBlock *> Removed);
|
|
void invalidateTraces();
|
|
bool shouldConvert();
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
char AArch64ConditionalCompares::ID = 0;
|
|
|
|
namespace llvm {
|
|
void initializeAArch64ConditionalComparesPass(PassRegistry &);
|
|
}
|
|
|
|
INITIALIZE_PASS_BEGIN(AArch64ConditionalCompares, "aarch64-ccmp",
|
|
"AArch64 CCMP Pass", false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
|
|
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
|
INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics)
|
|
INITIALIZE_PASS_END(AArch64ConditionalCompares, "aarch64-ccmp",
|
|
"AArch64 CCMP Pass", false, false)
|
|
|
|
FunctionPass *llvm::createAArch64ConditionalCompares() {
|
|
return new AArch64ConditionalCompares();
|
|
}
|
|
|
|
void AArch64ConditionalCompares::getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.addRequired<MachineBranchProbabilityInfo>();
|
|
AU.addRequired<MachineDominatorTree>();
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
AU.addRequired<MachineLoopInfo>();
|
|
AU.addPreserved<MachineLoopInfo>();
|
|
AU.addRequired<MachineTraceMetrics>();
|
|
AU.addPreserved<MachineTraceMetrics>();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
/// Update the dominator tree after if-conversion erased some blocks.
|
|
void AArch64ConditionalCompares::updateDomTree(
|
|
ArrayRef<MachineBasicBlock *> Removed) {
|
|
// convert() removes CmpBB which was previously dominated by Head.
|
|
// CmpBB children should be transferred to Head.
|
|
MachineDomTreeNode *HeadNode = DomTree->getNode(CmpConv.Head);
|
|
for (unsigned i = 0, e = Removed.size(); i != e; ++i) {
|
|
MachineDomTreeNode *Node = DomTree->getNode(Removed[i]);
|
|
assert(Node != HeadNode && "Cannot erase the head node");
|
|
assert(Node->getIDom() == HeadNode && "CmpBB should be dominated by Head");
|
|
while (Node->getNumChildren())
|
|
DomTree->changeImmediateDominator(Node->getChildren().back(), HeadNode);
|
|
DomTree->eraseNode(Removed[i]);
|
|
}
|
|
}
|
|
|
|
/// Update LoopInfo after if-conversion.
|
|
void
|
|
AArch64ConditionalCompares::updateLoops(ArrayRef<MachineBasicBlock *> Removed) {
|
|
if (!Loops)
|
|
return;
|
|
for (unsigned i = 0, e = Removed.size(); i != e; ++i)
|
|
Loops->removeBlock(Removed[i]);
|
|
}
|
|
|
|
/// Invalidate MachineTraceMetrics before if-conversion.
|
|
void AArch64ConditionalCompares::invalidateTraces() {
|
|
Traces->invalidate(CmpConv.Head);
|
|
Traces->invalidate(CmpConv.CmpBB);
|
|
}
|
|
|
|
/// Apply cost model and heuristics to the if-conversion in IfConv.
|
|
/// Return true if the conversion is a good idea.
|
|
///
|
|
bool AArch64ConditionalCompares::shouldConvert() {
|
|
// Stress testing mode disables all cost considerations.
|
|
if (Stress)
|
|
return true;
|
|
if (!MinInstr)
|
|
MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
|
|
|
|
// Head dominates CmpBB, so it is always included in its trace.
|
|
MachineTraceMetrics::Trace Trace = MinInstr->getTrace(CmpConv.CmpBB);
|
|
|
|
// If code size is the main concern
|
|
if (MinSize) {
|
|
int CodeSizeDelta = CmpConv.expectedCodeSizeDelta();
|
|
DEBUG(dbgs() << "Code size delta: " << CodeSizeDelta << '\n');
|
|
// If we are minimizing the code size, do the conversion whatever
|
|
// the cost is.
|
|
if (CodeSizeDelta < 0)
|
|
return true;
|
|
if (CodeSizeDelta > 0) {
|
|
DEBUG(dbgs() << "Code size is increasing, give up on this one.\n");
|
|
return false;
|
|
}
|
|
// CodeSizeDelta == 0, continue with the regular heuristics
|
|
}
|
|
|
|
// Heuristic: The compare conversion delays the execution of the branch
|
|
// instruction because we must wait for the inputs to the second compare as
|
|
// well. The branch has no dependent instructions, but delaying it increases
|
|
// the cost of a misprediction.
|
|
//
|
|
// Set a limit on the delay we will accept.
|
|
unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4;
|
|
|
|
// Instruction depths can be computed for all trace instructions above CmpBB.
|
|
unsigned HeadDepth =
|
|
Trace.getInstrCycles(CmpConv.Head->getFirstTerminator()).Depth;
|
|
unsigned CmpBBDepth =
|
|
Trace.getInstrCycles(CmpConv.CmpBB->getFirstTerminator()).Depth;
|
|
DEBUG(dbgs() << "Head depth: " << HeadDepth
|
|
<< "\nCmpBB depth: " << CmpBBDepth << '\n');
|
|
if (CmpBBDepth > HeadDepth + DelayLimit) {
|
|
DEBUG(dbgs() << "Branch delay would be larger than " << DelayLimit
|
|
<< " cycles.\n");
|
|
return false;
|
|
}
|
|
|
|
// Check the resource depth at the bottom of CmpBB - these instructions will
|
|
// be speculated.
|
|
unsigned ResDepth = Trace.getResourceDepth(true);
|
|
DEBUG(dbgs() << "Resources: " << ResDepth << '\n');
|
|
|
|
// Heuristic: The speculatively executed instructions must all be able to
|
|
// merge into the Head block. The Head critical path should dominate the
|
|
// resource cost of the speculated instructions.
|
|
if (ResDepth > HeadDepth) {
|
|
DEBUG(dbgs() << "Too many instructions to speculate.\n");
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) {
|
|
bool Changed = false;
|
|
while (CmpConv.canConvert(MBB) && shouldConvert()) {
|
|
invalidateTraces();
|
|
SmallVector<MachineBasicBlock *, 4> RemovedBlocks;
|
|
CmpConv.convert(RemovedBlocks);
|
|
Changed = true;
|
|
updateDomTree(RemovedBlocks);
|
|
updateLoops(RemovedBlocks);
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
|
|
DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
|
|
<< "********** Function: " << MF.getName() << '\n');
|
|
TII = MF.getSubtarget().getInstrInfo();
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
|
SchedModel = MF.getSubtarget().getSchedModel();
|
|
MRI = &MF.getRegInfo();
|
|
DomTree = &getAnalysis<MachineDominatorTree>();
|
|
Loops = getAnalysisIfAvailable<MachineLoopInfo>();
|
|
Traces = &getAnalysis<MachineTraceMetrics>();
|
|
MinInstr = nullptr;
|
|
MinSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
|
|
|
|
bool Changed = false;
|
|
CmpConv.runOnMachineFunction(MF);
|
|
|
|
// Visit blocks in dominator tree pre-order. The pre-order enables multiple
|
|
// cmp-conversions from the same head block.
|
|
// Note that updateDomTree() modifies the children of the DomTree node
|
|
// currently being visited. The df_iterator supports that; it doesn't look at
|
|
// child_begin() / child_end() until after a node has been visited.
|
|
for (auto *I : depth_first(DomTree))
|
|
if (tryConvert(I->getBlock()))
|
|
Changed = true;
|
|
|
|
return Changed;
|
|
}
|