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2aeb4771a6
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.9 KiB
LLVM
48 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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define float @test_vrecpss_f32(float %a, float %b) {
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; CHECK: test_vrecpss_f32
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; CHECK: frecps {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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%1 = insertelement <1 x float> undef, float %a, i32 0
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%2 = insertelement <1 x float> undef, float %b, i32 0
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%3 = call <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float> %1, <1 x float> %2)
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%4 = extractelement <1 x float> %3, i32 0
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ret float %4
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}
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define double @test_vrecpsd_f64(double %a, double %b) {
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; CHECK: test_vrecpsd_f64
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; CHECK: frecps {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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%1 = insertelement <1 x double> undef, double %a, i32 0
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%2 = insertelement <1 x double> undef, double %b, i32 0
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%3 = call <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double> %1, <1 x double> %2)
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%4 = extractelement <1 x double> %3, i32 0
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ret double %4
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}
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declare <1 x float> @llvm.arm.neon.vrecps.v1f32(<1 x float>, <1 x float>)
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declare <1 x double> @llvm.arm.neon.vrecps.v1f64(<1 x double>, <1 x double>)
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define float @test_vrsqrtss_f32(float %a, float %b) {
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; CHECK: test_vrsqrtss_f32
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; CHECK: frsqrts {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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%1 = insertelement <1 x float> undef, float %a, i32 0
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%2 = insertelement <1 x float> undef, float %b, i32 0
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%3 = call <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float> %1, <1 x float> %2)
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%4 = extractelement <1 x float> %3, i32 0
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ret float %4
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}
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define double @test_vrsqrtsd_f64(double %a, double %b) {
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; CHECK: test_vrsqrtsd_f64
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; CHECK: frsqrts {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
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%1 = insertelement <1 x double> undef, double %a, i32 0
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%2 = insertelement <1 x double> undef, double %b, i32 0
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%3 = call <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double> %1, <1 x double> %2)
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%4 = extractelement <1 x double> %3, i32 0
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ret double %4
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}
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declare <1 x float> @llvm.arm.neon.vrsqrts.v1f32(<1 x float>, <1 x float>)
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declare <1 x double> @llvm.arm.neon.vrsqrts.v1f64(<1 x double>, <1 x double>)
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