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54328c772c
v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193621 91177308-0d34-0410-b5e6-96231b3b80d8
122 lines
3.8 KiB
TableGen
122 lines
3.8 KiB
TableGen
//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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// Include AMDIL TD files
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include "AMDILBase.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features
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//===----------------------------------------------------------------------===//
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// Debugging Features
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"DumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter">;
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def FeatureIRStructurizer : SubtargetFeature <"EnableIRStructurizer",
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"EnableIRStructurizer",
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"true",
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"Enable IR Structurizer">;
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// Target features
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def FeatureFP64 : SubtargetFeature<"fp64",
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"FP64",
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"true",
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"Enable 64bit double precision operations">;
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def Feature64BitPtr : SubtargetFeature<"64BitPtr",
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"Is64bit",
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"true",
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"Specify if 64bit addressing should be used.">;
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def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
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"Is32on64bit",
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"false",
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"Specify if 64bit sized pointers with 32bit addressing should be used.">;
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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"R600ALUInst",
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"false",
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"Older version of ALU instructions encoding.">;
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def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
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"HasVertexCache",
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"true",
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"Specify use of dedicated vertex cache.">;
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def FeatureCaymanISA : SubtargetFeature<"caymanISA",
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"CaymanISA",
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"true",
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"Use Cayman ISA">;
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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Value,
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"Limit the maximum number of fetches in a clause to "#Value>;
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def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
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def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
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class SubtargetFeatureGeneration <string Value,
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list<SubtargetFeature> Implies> :
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SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
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Value#" GPU generation", Implies>;
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def FeatureR600 : SubtargetFeatureGeneration<"R600",
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[FeatureR600ALUInst, FeatureFetchLimit8]>;
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def FeatureR700 : SubtargetFeatureGeneration<"R700",
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[FeatureFetchLimit16]>;
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def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
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[FeatureFetchLimit16]>;
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def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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[FeatureFetchLimit16]>;
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def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
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[Feature64BitPtr, FeatureFP64]>;
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def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
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[Feature64BitPtr, FeatureFP64]>;
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//===----------------------------------------------------------------------===//
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def AMDGPUInstrInfo : InstrInfo {
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let guessInstructionProperties = 1;
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def AMDGPUAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int Variant = 0;
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bit isMCAsmWriter = 1;
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}
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def AMDGPU : Target {
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// Pull in Instruction Info:
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let InstructionSet = AMDGPUInstrInfo;
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let AssemblyWriters = [AMDGPUAsmWriter];
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}
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// Include AMDGPU TD files
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include "R600Schedule.td"
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include "SISchedule.td"
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include "Processors.td"
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include "AMDGPUInstrInfo.td"
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include "AMDGPUIntrinsics.td"
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include "AMDGPURegisterInfo.td"
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include "AMDGPUInstructions.td"
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include "AMDGPUCallingConv.td"
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