Owen Anderson 1f24002ed4 Fix incorrect disassembly test. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8		2011-09-23 22:05:54 +00:00
..
arm-tests.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
basic-arm-instructions.txt	Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.	2011-08-26 23:32:08 +00:00
dg.exp
fp-encoding.txt
invalid-Bcc-thumb.txt
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt
invalid-DSB-arm.txt
invalid-IT-CBNZ-thumb.txt	Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.	2011-09-08 22:42:49 +00:00
invalid-IT-thumb.txt	Add a testcase for r138625.	2011-08-26 06:45:08 +00:00
invalid-LDC-form-arm.txt
invalid-LDM-thumb.txt	LDM writeback is not allowed if Rn is in the target register list.	2011-09-09 23:13:33 +00:00
invalid-LDR_POST-arm.txt
invalid-LDR_PRE-arm.txt	invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.	2011-08-26 20:43:14 +00:00
invalid-LDRB_POST-arm.txt
invalid-LDRD_PRE-thumb.txt	Thumb2 assembly parsing and encoding for LDRD(immediate).	2011-09-08 22:07:06 +00:00
invalid-LDRD-arm.txt
invalid-LDRrs-arm.txt
invalid-LDRT-arm.txt
invalid-LSL-regform.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-RSC-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-SSAT-arm.txt
invalid-STMIA_UPD-thumb.txt
invalid-STRBrs-arm.txt
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt
invalid-t2LDRBT-thumb.txt
invalid-t2LDREXD-thumb.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
invalid-t2LDRSHi8-thumb.txt
invalid-t2LDRSHi12-thumb.txt
invalid-t2PUSH-thumb.txt	Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.	2011-09-12 21:28:46 +00:00
invalid-t2STR_POST-thumb.txt
invalid-t2STRD_PRE-thumb.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
invalid-t2STREXB-thumb.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
invalid-t2STREXD-thumb.txt
invalid-UMAAL-arm.txt
invalid-UQADD8-arm.txt
invalid-VLD1DUPq8_UPD-arm.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
invalid-VLD3DUPd32_UPD-thumb.txt
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
invalid-VST2b32_UPD-arm.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
memory-arm-instructions.txt
neon-tests.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
neon.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
neont2.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
thumb1.txt	Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.	2011-08-26 18:09:22 +00:00
thumb2.txt	Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.	2011-09-23 21:26:40 +00:00
thumb-printf.txt	Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.	2011-09-07 19:42:28 +00:00
thumb-tests.txt	Fix incorrect disassembly test.	2011-09-23 22:05:54 +00:00