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https://github.com/c64scene-ar/llvm-6502.git
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461f1fc359
The theory is it's still faster than a pair of movq / a quad of movl. This will probably hurt older chips like P4 but should run faster on current and future Intel processors. rdar://8817010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122955 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
1.0 KiB
LLVM
27 lines
1.0 KiB
LLVM
; RUN: llc < %s -combiner-alias-analysis -march=x86-64 | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.4"
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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define fastcc i32 @cli_magic_scandesc(i8* %in) nounwind ssp {
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entry:
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%a = alloca [64 x i8]
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%b = getelementptr inbounds [64 x i8]* %a, i64 0, i32 0
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%c = getelementptr inbounds [64 x i8]* %a, i64 0, i32 30
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%d = load i8* %b, align 8
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%e = load i8* %c, align 8
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%f = bitcast [64 x i8]* %a to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %f, i8* %in, i64 64, i32 8, i1 false) nounwind
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store i8 %d, i8* %b, align 8
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store i8 %e, i8* %c, align 8
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ret i32 0
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}
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; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip), %rax
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; CHECK: movb 30(%rsp), %cl
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; CHECK: movb (%rsp), %dl
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; CHECK: movb %dl, (%rsp)
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; CHECK: movb %cl, 30(%rsp)
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; CHECK: callq ___stack_chk_fail
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