mirror of
https://github.com/c64scene-ar/llvm-6502.git
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461f1fc359
The theory is it's still faster than a pair of movq / a quad of movl. This will probably hurt older chips like P4 but should run faster on current and future Intel processors. rdar://8817010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122955 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.3 KiB
LLVM
54 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=i386-apple-darwin < %s | FileCheck %s
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declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
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define fastcc void @t1() nounwind {
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entry:
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; CHECK: t1:
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; CHECK: pxor %xmm0, %xmm0
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; CHECK: movups %xmm0, 160
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; CHECK: movups %xmm0, 144
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; CHECK: movups %xmm0, 128
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; CHECK: movups %xmm0, 112
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; CHECK: movups %xmm0, 96
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; CHECK: movups %xmm0, 80
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; CHECK: movups %xmm0, 64
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; CHECK: movups %xmm0, 48
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; CHECK: movups %xmm0, 32
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; CHECK: movups %xmm0, 16
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; CHECK: movups %xmm0, 0
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; CHECK: movl $0, 184
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; CHECK: movl $0, 180
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; CHECK: movl $0, 176
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call void @llvm.memset.i32( i8* null, i8 0, i32 188, i32 1 ) nounwind
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unreachable
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}
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define fastcc void @t2(i8 signext %c) nounwind {
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entry:
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; CHECK: t2:
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; CHECK: calll _memset
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call void @llvm.memset.i32( i8* undef, i8 %c, i32 76, i32 1 ) nounwind
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unreachable
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}
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declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
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define void @t3(i8* nocapture %s, i8 %a) nounwind {
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entry:
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tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false)
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ret void
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; CHECK: t3:
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; CHECK: imull $16843009
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}
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define void @t4(i8* nocapture %s, i8 %a) nounwind {
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entry:
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tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false)
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ret void
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; CHECK: t4:
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; CHECK: imull $16843009
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; CHECK-NOT: imul
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; CHECK: ret
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}
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