mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-15 20:06:46 +00:00
608034ec1a
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15975 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.4 KiB
TableGen
41 lines
1.4 KiB
TableGen
//===- PPC32RegisterInfo.td - The PowerPC32 Register File --*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file was developed by the LLVM research group and is distributed under
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "PowerPCRegisterInfo.td"
|
|
|
|
/// Register classes
|
|
// Allocate volatiles first
|
|
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
|
|
def GPRC : RegisterClass<i32, 32,
|
|
[R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
|
|
R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
|
|
R16, R15, R14, R13, R31, R0, R1, LR]>
|
|
{
|
|
let Methods = [{
|
|
iterator allocation_order_begin(MachineFunction &MF) const {
|
|
return begin() + (AIX ? 1 : 0);
|
|
}
|
|
iterator allocation_order_end(MachineFunction &MF) const {
|
|
if (hasFP(MF))
|
|
return end()-4;
|
|
else
|
|
return end()-3;
|
|
}
|
|
}];
|
|
}
|
|
|
|
def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
|
|
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
|
|
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
|
|
|
|
def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;
|