Daniel Sanders 1f4c755c2c [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 ... Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-12 15:00:17 +00:00
..
AArch64	[AArch64] Basic Sched Model for Cortex-A57.	2014-06-11 21:06:56 +00:00
ARM	Global merge for global symbols.	2014-06-11 06:44:53 +00:00
CPP	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Generic	Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.	2014-06-05 19:29:43 +00:00
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6	2014-06-12 15:00:17 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
NVPTX	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
PowerPC	[PPC64LE] Recognize shufflevector patterns for little endian	2014-06-10 14:35:01 +00:00
R600	R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*	2014-06-12 08:21:54 +00:00
SPARC	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Thumb	Fix a bug in the Thumb1 ARM Load/Store optimizer	2014-06-10 16:39:21 +00:00
Thumb2	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
X86	[X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit vectors.	2014-06-12 10:53:48 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00