llvm-6502/lib/Target/Sparc
Tim Northover 049ffbbdf2 TableGen: allow use of uint64_t for available features mask.
ARM in particular is getting dangerously close to exceeding 32 bits worth of
possible subtarget features. When this happens, various parts of MC start to
fail inexplicably as masks get truncated to "unsigned".

Mostly just refactoring at present, and there's probably no way to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-18 11:49:42 +00:00
..
AsmParser TableGen: allow use of uint64_t for available features mask. 2014-08-18 11:49:42 +00:00
Disassembler Prune dependency to MC from each target disassembler. 2014-07-24 11:45:11 +00:00
InstPrinter Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
MCTargetDesc Remove HasLEB128. 2014-08-15 14:01:07 +00:00
TargetInfo
CMakeLists.txt Temporarily Revert "Nuke the old JIT." as it's not quite ready to 2014-08-07 22:02:54 +00:00
DelaySlotFiller.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
LLVMBuild.txt
Makefile Temporarily Revert "Nuke the old JIT." as it's not quite ready to 2014-08-07 22:02:54 +00:00
README.txt
Sparc.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
Sparc.td
SparcAsmPrinter.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SparcCallingConv.td
SparcCodeEmitter.cpp Temporarily Revert "Nuke the old JIT." as it's not quite ready to 2014-08-07 22:02:54 +00:00
SparcFrameLowering.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SparcFrameLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcInstr64Bit.td Sparc: disable printing on longer "brX,pt" aliases 2014-05-16 09:41:35 +00:00
SparcInstrAliases.td Sparc: disable printing of jmp/call aliases (C++ does it) 2014-05-16 09:41:39 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcInstrInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcInstrInfo.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcInstrVIS.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcISelDAGToDAG.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SparcISelLowering.cpp Remove the target machine from CCState. Previously it was only used 2014-08-06 18:45:26 +00:00
SparcISelLowering.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcJITInfo.cpp Temporarily Revert "Nuke the old JIT." as it's not quite ready to 2014-08-07 22:02:54 +00:00
SparcJITInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcMCInstLower.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcRegisterInfo.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SparcRegisterInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcRegisterInfo.td
SparcRelocations.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcSelectionDAGInfo.cpp Have SparcSelectionDAGInfo take a DataLayout to initialize since 2014-06-26 22:33:52 +00:00
SparcSelectionDAGInfo.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcSubtarget.cpp Move the various Subtarget dependent members down to the subtarget 2014-06-26 22:33:55 +00:00
SparcSubtarget.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcTargetMachine.cpp Temporarily Revert "Nuke the old JIT." as it's not quite ready to 2014-08-07 22:02:54 +00:00
SparcTargetMachine.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcTargetObjectFile.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcTargetObjectFile.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00
SparcTargetStreamer.h Canonicalize header guards into a common format. 2014-08-13 16:26:38 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.