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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
2.6 KiB
LLVM
93 lines
2.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}test_i64_eq:
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; SI: v_cmp_eq_i64
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define void @test_i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp eq i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_ne:
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; SI: v_cmp_ne_i64
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define void @test_i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ne i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_slt:
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; SI: v_cmp_lt_i64
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define void @test_i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp slt i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_ult:
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; SI: v_cmp_lt_u64
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define void @test_i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ult i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_sle:
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; SI: v_cmp_le_i64
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define void @test_i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp sle i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_ule:
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; SI: v_cmp_le_u64
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define void @test_i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ule i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_sgt:
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; SI: v_cmp_gt_i64
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define void @test_i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp sgt i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_ugt:
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; SI: v_cmp_gt_u64
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define void @test_i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp ugt i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_sge:
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; SI: v_cmp_ge_i64
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define void @test_i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp sge i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_i64_uge:
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; SI: v_cmp_ge_u64
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define void @test_i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%cmp = icmp uge i64 %a, %b
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%result = sext i1 %cmp to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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