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CodeGenPrepare uses extensively TargetLowering which is part of libLLVMCodeGen. This is a layer violation which would introduce eventually a dependence on CodeGen in ScalarOpts. Move CodeGenPrepare into libLLVMCodeGen to avoid that. Follow-up of <rdar://problem/15519855> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201912 91177308-0d34-0410-b5e6-96231b3b80d8
593 lines
22 KiB
C++
593 lines
22 KiB
C++
//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines interfaces to access the target independent code generation
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// passes provided by the LLVM backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_PASSES_H
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#define LLVM_CODEGEN_PASSES_H
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#include "llvm/Pass.h"
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#include "llvm/Target/TargetMachine.h"
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#include <string>
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namespace llvm {
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class FunctionPass;
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class MachineFunctionPass;
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class PassConfigImpl;
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class PassInfo;
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class ScheduleDAGInstrs;
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class TargetLowering;
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class TargetLoweringBase;
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class TargetRegisterClass;
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class raw_ostream;
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struct MachineSchedContext;
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// The old pass manager infrastructure is hidden in a legacy namespace now.
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namespace legacy {
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class PassManagerBase;
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}
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using legacy::PassManagerBase;
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/// Discriminated union of Pass ID types.
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///
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/// The PassConfig API prefers dealing with IDs because they are safer and more
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/// efficient. IDs decouple configuration from instantiation. This way, when a
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/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
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/// refer to a Pass pointer after adding it to a pass manager, which deletes
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/// redundant pass instances.
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///
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/// However, it is convient to directly instantiate target passes with
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/// non-default ctors. These often don't have a registered PassInfo. Rather than
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/// force all target passes to implement the pass registry boilerplate, allow
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/// the PassConfig API to handle either type.
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///
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/// AnalysisID is sadly char*, so PointerIntPair won't work.
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class IdentifyingPassPtr {
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union {
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AnalysisID ID;
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Pass *P;
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};
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bool IsInstance;
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public:
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IdentifyingPassPtr() : P(0), IsInstance(false) {}
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IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
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IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
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bool isValid() const { return P; }
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bool isInstance() const { return IsInstance; }
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AnalysisID getID() const {
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assert(!IsInstance && "Not a Pass ID");
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return ID;
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}
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Pass *getInstance() const {
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assert(IsInstance && "Not a Pass Instance");
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return P;
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}
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};
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template <> struct isPodLike<IdentifyingPassPtr> {
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static const bool value = true;
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};
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/// Target-Independent Code Generator Pass Configuration Options.
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///
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/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
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/// to the internals of other CodeGen passes.
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class TargetPassConfig : public ImmutablePass {
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public:
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/// Pseudo Pass IDs. These are defined within TargetPassConfig because they
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/// are unregistered pass IDs. They are only useful for use with
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/// TargetPassConfig APIs to identify multiple occurrences of the same pass.
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///
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/// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
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/// during codegen, on SSA form.
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static char EarlyTailDuplicateID;
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/// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
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/// optimization after regalloc.
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static char PostRAMachineLICMID;
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private:
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PassManagerBase *PM;
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AnalysisID StartAfter;
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AnalysisID StopAfter;
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bool Started;
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bool Stopped;
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protected:
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TargetMachine *TM;
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PassConfigImpl *Impl; // Internal data structures
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bool Initialized; // Flagged after all passes are configured.
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// Target Pass Options
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// Targets provide a default setting, user flags override.
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//
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bool DisableVerify;
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/// Default setting for -enable-tail-merge on this target.
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bool EnableTailMerge;
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public:
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TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
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// Dummy constructor.
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TargetPassConfig();
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virtual ~TargetPassConfig();
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static char ID;
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/// Get the right type of TargetMachine for this target.
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template<typename TMC> TMC &getTM() const {
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return *static_cast<TMC*>(TM);
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}
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const TargetLowering *getTargetLowering() const {
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return TM->getTargetLowering();
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}
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//
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void setInitialized() { Initialized = true; }
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CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
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/// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
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/// running only a portion of the normal code-gen pass sequence. If the
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/// Start pass ID is zero, then compilation will begin at the normal point;
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/// otherwise, clear the Started flag to indicate that passes should not be
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/// added until the starting pass is seen. If the Stop pass ID is zero,
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/// then compilation will continue to the end.
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void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
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StartAfter = Start;
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StopAfter = Stop;
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Started = (StartAfter == 0);
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}
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void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
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bool getEnableTailMerge() const { return EnableTailMerge; }
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void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
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/// Allow the target to override a specific pass without overriding the pass
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/// pipeline. When passes are added to the standard pipeline at the
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/// point where StandardID is expected, add TargetID in its place.
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void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
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/// Insert InsertedPassID pass after TargetPassID pass.
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void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
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/// Allow the target to enable a specific standard pass by default.
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void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
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/// Allow the target to disable a specific standard pass by default.
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void disablePass(AnalysisID PassID) {
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substitutePass(PassID, IdentifyingPassPtr());
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}
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/// Return the pass substituted for StandardID by the target.
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/// If no substitution exists, return StandardID.
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IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
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/// Return true if the optimized regalloc pipeline is enabled.
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bool getOptimizeRegAlloc() const;
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/// Add common target configurable passes that perform LLVM IR to IR
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/// transforms following machine independent optimization.
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virtual void addIRPasses();
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/// Add passes to lower exception handling for the code generator.
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void addPassesToHandleExceptions();
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/// Add pass to prepare the LLVM IR for code generation. This should be done
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/// before exception handling preparation passes.
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virtual void addCodeGenPrepare();
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/// Add common passes that perform LLVM IR to IR transforms in preparation for
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/// instruction selection.
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virtual void addISelPrepare();
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/// addInstSelector - This method should install an instruction selector pass,
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/// which converts from LLVM code to machine instructions.
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virtual bool addInstSelector() {
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return true;
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}
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/// Add the complete, standard set of LLVM CodeGen passes.
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/// Fully developed targets will not generally override this.
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virtual void addMachinePasses();
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/// Create an instance of ScheduleDAGInstrs to be run within the standard
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/// MachineScheduler pass for this function and target at the current
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/// optimization level.
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///
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/// This can also be used to plug a new MachineSchedStrategy into an instance
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/// of the standard ScheduleDAGMI:
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/// return new ScheduleDAGMI(C, new MyStrategy(C))
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///
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/// Return NULL to select the default (generic) machine scheduler.
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virtual ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const {
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return 0;
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}
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/// Similar to createMachineScheduler but used when postRA machine scheduling
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/// is enabled.
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virtual ScheduleDAGInstrs *
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createPostMachineScheduler(MachineSchedContext *C) const {
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return 0;
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}
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protected:
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// Helper to verify the analysis is really immutable.
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void setOpt(bool &Opt, bool Val);
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/// Methods with trivial inline returns are convenient points in the common
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/// codegen pass pipeline where targets may insert passes. Methods with
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/// out-of-line standard implementations are major CodeGen stages called by
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/// addMachinePasses. Some targets may override major stages when inserting
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/// passes is insufficient, but maintaining overriden stages is more work.
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///
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/// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
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/// passes (which are run just before instruction selector).
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virtual bool addPreISel() {
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return true;
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}
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/// addMachineSSAOptimization - Add standard passes that optimize machine
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/// instructions in SSA form.
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virtual void addMachineSSAOptimization();
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/// Add passes that optimize instruction level parallelism for out-of-order
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/// targets. These passes are run while the machine code is still in SSA
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/// form, so they can use MachineTraceMetrics to control their heuristics.
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///
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/// All passes added here should preserve the MachineDominatorTree,
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/// MachineLoopInfo, and MachineTraceMetrics analyses.
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virtual bool addILPOpts() {
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return false;
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}
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/// addPreRegAlloc - This method may be implemented by targets that want to
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/// run passes immediately before register allocation. This should return
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/// true if -print-machineinstrs should print after these passes.
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virtual bool addPreRegAlloc() {
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return false;
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}
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/// createTargetRegisterAllocator - Create the register allocator pass for
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/// this target at the current optimization level.
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virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
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/// addFastRegAlloc - Add the minimum set of target-independent passes that
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/// are required for fast register allocation.
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virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
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/// addOptimizedRegAlloc - Add passes related to register allocation.
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/// LLVMTargetMachine provides standard regalloc passes for most targets.
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virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
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/// addPreRewrite - Add passes to the optimized register allocation pipeline
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/// after register allocation is complete, but before virtual registers are
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/// rewritten to physical registers.
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///
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/// These passes must preserve VirtRegMap and LiveIntervals, and when running
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/// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
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/// When these passes run, VirtRegMap contains legal physreg assignments for
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/// all virtual registers.
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virtual bool addPreRewrite() {
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return false;
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}
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/// addPostRegAlloc - This method may be implemented by targets that want to
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/// run passes after register allocation pass pipeline but before
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/// prolog-epilog insertion. This should return true if -print-machineinstrs
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/// should print after these passes.
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virtual bool addPostRegAlloc() {
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return false;
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}
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/// Add passes that optimize machine instructions after register allocation.
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virtual void addMachineLateOptimization();
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/// addPreSched2 - This method may be implemented by targets that want to
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/// run passes after prolog-epilog insertion and before the second instruction
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/// scheduling pass. This should return true if -print-machineinstrs should
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/// print after these passes.
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virtual bool addPreSched2() {
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return false;
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}
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/// addGCPasses - Add late codegen passes that analyze code for garbage
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/// collection. This should return true if GC info should be printed after
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/// these passes.
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virtual bool addGCPasses();
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/// Add standard basic block placement passes.
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virtual void addBlockPlacement();
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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virtual bool addPreEmitPass() {
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return false;
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}
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/// Utilities for targets to add passes to the pass manager.
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///
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/// Add a CodeGen pass at this point in the pipeline after checking overrides.
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/// Return the pass that was added, or zero if no pass was added.
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AnalysisID addPass(AnalysisID PassID);
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/// Add a pass to the PassManager if that pass is supposed to be run, as
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/// determined by the StartAfter and StopAfter options. Takes ownership of the
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/// pass.
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void addPass(Pass *P);
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/// addMachinePasses helper to create the target-selected or overriden
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/// regalloc pass.
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FunctionPass *createRegAllocPass(bool Optimized);
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/// printAndVerify - Add a pass to dump then verify the machine function, if
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/// those steps are enabled.
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///
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void printAndVerify(const char *Banner);
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};
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} // namespace llvm
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/// List of target independent CodeGen pass IDs.
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namespace llvm {
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/// \brief Create a basic TargetTransformInfo analysis pass.
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///
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/// This pass implements the target transform info analysis using the target
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/// independent information available to the LLVM code generator.
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ImmutablePass *
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createBasicTargetTransformInfoPass(const TargetMachine *TM);
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/// createUnreachableBlockEliminationPass - The LLVM code generator does not
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/// work well with unreachable basic blocks (what live ranges make sense for a
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/// block that cannot be reached?). As such, a code generator should either
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/// not instruction select unreachable blocks, or run this pass as its
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/// last LLVM modifying pass to clean up blocks that are not reachable from
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/// the entry block.
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FunctionPass *createUnreachableBlockEliminationPass();
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/// MachineFunctionPrinter pass - This pass prints out the machine function to
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/// the given stream as a debugging tool.
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MachineFunctionPass *
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createMachineFunctionPrinterPass(raw_ostream &OS,
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const std::string &Banner ="");
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/// createCodeGenPreparePass - Transform the code to expose more pattern
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/// matching during instruction selection.
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FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = 0);
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/// MachineLoopInfo - This pass is a loop analysis pass.
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extern char &MachineLoopInfoID;
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/// MachineDominators - This pass is a machine dominators analysis pass.
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extern char &MachineDominatorsID;
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/// EdgeBundles analysis - Bundle machine CFG edges.
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extern char &EdgeBundlesID;
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/// LiveVariables pass - This pass computes the set of blocks in which each
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/// variable is life and sets machine operand kill flags.
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extern char &LiveVariablesID;
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/// PHIElimination - This pass eliminates machine instruction PHI nodes
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/// by inserting copy instructions. This destroys SSA information, but is the
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/// desired input for some register allocators. This pass is "required" by
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/// these register allocator like this: AU.addRequiredID(PHIEliminationID);
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extern char &PHIEliminationID;
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/// LiveIntervals - This analysis keeps track of the live ranges of virtual
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/// and physical registers.
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extern char &LiveIntervalsID;
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/// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
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extern char &LiveStacksID;
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/// TwoAddressInstruction - This pass reduces two-address instructions to
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/// use two operands. This destroys SSA information but it is desired by
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/// register allocators.
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extern char &TwoAddressInstructionPassID;
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/// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
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extern char &ProcessImplicitDefsID;
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/// RegisterCoalescer - This pass merges live ranges to eliminate copies.
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extern char &RegisterCoalescerID;
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/// MachineScheduler - This pass schedules machine instructions.
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extern char &MachineSchedulerID;
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/// PostMachineScheduler - This pass schedules machine instructions postRA.
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extern char &PostMachineSchedulerID;
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/// SpillPlacement analysis. Suggest optimal placement of spill code between
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/// basic blocks.
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extern char &SpillPlacementID;
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/// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
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/// assigned in VirtRegMap.
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extern char &VirtRegRewriterID;
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/// UnreachableMachineBlockElimination - This pass removes unreachable
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/// machine basic blocks.
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extern char &UnreachableMachineBlockElimID;
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/// DeadMachineInstructionElim - This pass removes dead machine instructions.
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extern char &DeadMachineInstructionElimID;
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/// FastRegisterAllocation Pass - This pass register allocates as fast as
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/// possible. It is best suited for debug code where live ranges are short.
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///
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FunctionPass *createFastRegisterAllocator();
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/// BasicRegisterAllocation Pass - This pass implements a degenerate global
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/// register allocator using the basic regalloc framework.
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///
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FunctionPass *createBasicRegisterAllocator();
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/// Greedy register allocation pass - This pass implements a global register
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/// allocator for optimized builds.
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///
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FunctionPass *createGreedyRegisterAllocator();
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/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
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/// Quadratic Prograaming (PBQP) based register allocator.
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///
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FunctionPass *createDefaultPBQPRegisterAllocator();
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/// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
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/// and eliminates abstract frame references.
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extern char &PrologEpilogCodeInserterID;
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/// ExpandPostRAPseudos - This pass expands pseudo instructions after
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/// register allocation.
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extern char &ExpandPostRAPseudosID;
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/// createPostRAScheduler - This pass performs post register allocation
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/// scheduling.
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extern char &PostRASchedulerID;
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/// BranchFolding - This pass performs machine code CFG based
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/// optimizations to delete branches to branches, eliminate branches to
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/// successor blocks (creating fall throughs), and eliminating branches over
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/// branches.
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extern char &BranchFolderPassID;
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/// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
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extern char &MachineFunctionPrinterPassID;
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/// TailDuplicate - Duplicate blocks with unconditional branches
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/// into tails of their predecessors.
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extern char &TailDuplicateID;
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/// MachineTraceMetrics - This pass computes critical path and CPU resource
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/// usage in an ensemble of traces.
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extern char &MachineTraceMetricsID;
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/// EarlyIfConverter - This pass performs if-conversion on SSA form by
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/// inserting cmov instructions.
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extern char &EarlyIfConverterID;
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/// StackSlotColoring - This pass performs stack coloring and merging.
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/// It merges disjoint allocas to reduce the stack size.
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extern char &StackColoringID;
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/// IfConverter - This pass performs machine code if conversion.
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extern char &IfConverterID;
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/// MachineBlockPlacement - This pass places basic blocks based on branch
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/// probabilities.
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extern char &MachineBlockPlacementID;
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/// MachineBlockPlacementStats - This pass collects statistics about the
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/// basic block placement using branch probabilities and block frequency
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/// information.
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extern char &MachineBlockPlacementStatsID;
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/// GCLowering Pass - Performs target-independent LLVM IR transformations for
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/// highly portable strategies.
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///
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FunctionPass *createGCLoweringPass();
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/// GCMachineCodeAnalysis - Target-independent pass to mark safe points
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/// in machine code. Must be added very late during code generation, just
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/// prior to output, and importantly after all CFG transformations (such as
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/// branch folding).
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extern char &GCMachineCodeAnalysisID;
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/// Creates a pass to print GC metadata.
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///
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FunctionPass *createGCInfoPrinter(raw_ostream &OS);
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/// MachineCSE - This pass performs global CSE on machine instructions.
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extern char &MachineCSEID;
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/// MachineLICM - This pass performs LICM on machine instructions.
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extern char &MachineLICMID;
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/// MachineSinking - This pass performs sinking on machine instructions.
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extern char &MachineSinkingID;
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/// MachineCopyPropagation - This pass performs copy propagation on
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/// machine instructions.
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extern char &MachineCopyPropagationID;
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/// PeepholeOptimizer - This pass performs peephole optimizations -
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/// like extension and comparison eliminations.
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extern char &PeepholeOptimizerID;
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/// OptimizePHIs - This pass optimizes machine instruction PHIs
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/// to take advantage of opportunities created during DAG legalization.
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extern char &OptimizePHIsID;
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/// StackSlotColoring - This pass performs stack slot coloring.
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extern char &StackSlotColoringID;
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/// createStackProtectorPass - This pass adds stack protectors to functions.
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///
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FunctionPass *createStackProtectorPass(const TargetMachine *TM);
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/// createMachineVerifierPass - This pass verifies cenerated machine code
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/// instructions for correctness.
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///
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FunctionPass *createMachineVerifierPass(const char *Banner = 0);
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/// createDwarfEHPass - This pass mulches exception handling code into a form
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/// adapted to code generation. Required if using dwarf exception handling.
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FunctionPass *createDwarfEHPass(const TargetMachine *TM);
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/// createSjLjEHPreparePass - This pass adapts exception handling code to use
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/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
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///
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FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM);
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/// LocalStackSlotAllocation - This pass assigns local frame indices to stack
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/// slots relative to one another and allocates base registers to access them
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/// when it is estimated by the target to be out of range of normal frame
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/// pointer or stack pointer index addressing.
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extern char &LocalStackSlotAllocationID;
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/// ExpandISelPseudos - This pass expands pseudo-instructions.
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extern char &ExpandISelPseudosID;
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/// createExecutionDependencyFixPass - This pass fixes execution time
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/// problems with dependent instructions, such as switching execution
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/// domains to match.
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///
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/// The pass will examine instructions using and defining registers in RC.
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///
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FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
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/// UnpackMachineBundles - This pass unpack machine instruction bundles.
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extern char &UnpackMachineBundlesID;
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/// FinalizeMachineBundles - This pass finalize machine instruction
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/// bundles (created earlier, e.g. during pre-RA scheduling).
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extern char &FinalizeMachineBundlesID;
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/// StackMapLiveness - This pass analyses the register live-out set of
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/// stackmap/patchpoint intrinsics and attaches the calculated information to
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/// the intrinsic for later emission to the StackMap.
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extern char &StackMapLivenessID;
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} // End llvm namespace
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#endif
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