mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-04 07:29:20 +00:00
1fd36e41e4
form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178193 91177308-0d34-0410-b5e6-96231b3b80d8
332 lines
6.7 KiB
LLVM
332 lines
6.7 KiB
LLVM
; RUN: llc < %s -mtriple=i686-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32
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; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64
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define void @t1(i32 %x) nounwind ssp {
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entry:
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; 32: t1:
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; 32: jmp {{_?}}foo
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; 64: t1:
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; 64: jmp {{_?}}foo
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tail call void @foo() nounwind
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ret void
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}
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declare void @foo()
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define void @t2() nounwind ssp {
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entry:
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; 32: t2:
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; 32: jmp {{_?}}foo2
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; 64: t2:
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; 64: jmp {{_?}}foo2
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%0 = tail call i32 @foo2() nounwind
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ret void
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}
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declare i32 @foo2()
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define void @t3() nounwind ssp {
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entry:
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; 32: t3:
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; 32: jmp {{_?}}foo3
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; 64: t3:
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; 64: jmp {{_?}}foo3
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%0 = tail call i32 @foo3() nounwind
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ret void
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}
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declare i32 @foo3()
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define void @t4(void (i32)* nocapture %x) nounwind ssp {
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entry:
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; 32: t4:
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; 32: calll *
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; FIXME: gcc can generate a tailcall for this. But it's tricky.
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; 64: t4:
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; 64-NOT: call
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; 64: jmpq *
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tail call void %x(i32 0) nounwind
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ret void
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}
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define void @t5(void ()* nocapture %x) nounwind ssp {
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entry:
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; 32: t5:
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; 32-NOT: call
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; 32: jmpl *4(%esp)
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; 64: t5:
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; 64-NOT: call
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; 64: jmpq *%rdi
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tail call void %x() nounwind
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ret void
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}
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define i32 @t6(i32 %x) nounwind ssp {
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entry:
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; 32: t6:
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; 32: calll {{_?}}t6
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; 32: jmp {{_?}}bar
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; 64: t6:
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; 64: jmp {{_?}}t6
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; 64: jmp {{_?}}bar
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%0 = icmp slt i32 %x, 10
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br i1 %0, label %bb, label %bb1
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bb:
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%1 = add nsw i32 %x, -1
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%2 = tail call i32 @t6(i32 %1) nounwind ssp
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ret i32 %2
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bb1:
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%3 = tail call i32 @bar(i32 %x) nounwind
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ret i32 %3
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}
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declare i32 @bar(i32)
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define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
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entry:
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; 32: t7:
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; 32: jmp {{_?}}bar2
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; 64: t7:
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; 64: jmp {{_?}}bar2
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%0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
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ret i32 %0
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}
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declare i32 @bar2(i32, i32, i32)
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define signext i16 @t8() nounwind ssp {
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entry:
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; 32: t8:
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; 32: calll {{_?}}bar3
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; 64: t8:
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; 64: callq {{_?}}bar3
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%0 = tail call signext i16 @bar3() nounwind ; <i16> [#uses=1]
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ret i16 %0
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}
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declare signext i16 @bar3()
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define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
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entry:
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; 32: t9:
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; 32: calll *
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; 64: t9:
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; 64: callq *
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%0 = bitcast i32 (i32)* %x to i16 (i32)*
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%1 = tail call signext i16 %0(i32 0) nounwind
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ret i16 %1
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}
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define void @t10() nounwind ssp {
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entry:
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; 32: t10:
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; 32: calll
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; 64: t10:
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; 64: callq
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%0 = tail call i32 @foo4() noreturn nounwind
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unreachable
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}
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declare i32 @foo4()
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define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
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; In 32-bit mode, it's emitting a bunch of dead loads that are not being
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; eliminated currently.
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; 32: t11:
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; 32-NOT: subl ${{[0-9]+}}, %esp
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; 32: je
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; 32-NOT: movl
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; 32-NOT: addl ${{[0-9]+}}, %esp
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; 32: jmp {{_?}}foo5
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; 64: t11:
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; 64-NOT: subq ${{[0-9]+}}, %esp
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; 64-NOT: addq ${{[0-9]+}}, %esp
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; 64: jmp {{_?}}foo5
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entry:
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%0 = icmp eq i32 %x, 0
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br i1 %0, label %bb6, label %bb
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bb:
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%1 = tail call i32 @foo5(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind
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ret i32 %1
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bb6:
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ret i32 0
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}
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declare i32 @foo5(i32, i32, i32, i32, i32)
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%struct.t = type { i32, i32, i32, i32, i32 }
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define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
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; 32: t12:
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; 32-NOT: subl ${{[0-9]+}}, %esp
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; 32-NOT: addl ${{[0-9]+}}, %esp
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; 32: jmp {{_?}}foo6
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; 64: t12:
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; 64-NOT: subq ${{[0-9]+}}, %esp
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; 64-NOT: addq ${{[0-9]+}}, %esp
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; 64: jmp {{_?}}foo6
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entry:
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%0 = icmp eq i32 %x, 0
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br i1 %0, label %bb2, label %bb
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bb:
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%1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind
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ret i32 %1
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bb2:
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ret i32 0
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}
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declare i32 @foo6(i32, i32, %struct.t* byval align 4)
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; rdar://r7717598
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%struct.ns = type { i32, i32 }
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%struct.cp = type { float, float, float, float, float }
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define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
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; 32: t13:
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; 32-NOT: jmp
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; 32: calll
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; 32: ret
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; 64: t13:
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; 64-NOT: jmp
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; 64: callq
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; 64: ret
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entry:
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%0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind
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ret %struct.ns* %0
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}
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; rdar://6195379
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; llvm can't do sibcall for this in 32-bit mode (yet).
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declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp
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%struct.__block_descriptor = type { i64, i64 }
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%struct.__block_descriptor_withcopydispose = type { i64, i64, i8*, i8* }
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%struct.__block_literal_1 = type { i8*, i32, i32, i8*, %struct.__block_descriptor* }
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%struct.__block_literal_2 = type { i8*, i32, i32, i8*, %struct.__block_descriptor_withcopydispose*, void ()* }
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define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
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entry:
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; 64: t14:
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; 64: movq 32(%rdi)
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; 64-NOT: movq 16(%rdi)
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; 64: jmpq *16({{%rdi|%rax}})
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%0 = getelementptr inbounds %struct.__block_literal_2* %.block_descriptor, i64 0, i32 5 ; <void ()**> [#uses=1]
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%1 = load void ()** %0, align 8 ; <void ()*> [#uses=2]
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%2 = bitcast void ()* %1 to %struct.__block_literal_1* ; <%struct.__block_literal_1*> [#uses=1]
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%3 = getelementptr inbounds %struct.__block_literal_1* %2, i64 0, i32 3 ; <i8**> [#uses=1]
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%4 = load i8** %3, align 8 ; <i8*> [#uses=1]
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%5 = bitcast i8* %4 to void (i8*)* ; <void (i8*)*> [#uses=1]
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%6 = bitcast void ()* %1 to i8* ; <i8*> [#uses=1]
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tail call void %5(i8* %6) nounwind
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ret void
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}
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; rdar://7726868
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%struct.foo = type { [4 x i32] }
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define void @t15(%struct.foo* noalias sret %agg.result) nounwind {
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; 32: t15:
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; 32: calll {{_?}}f
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; 32: ret $4
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; 64: t15:
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; 64: callq {{_?}}f
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; 64: ret
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tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind
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ret void
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}
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declare void @f(%struct.foo* noalias sret) nounwind
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define void @t16() nounwind ssp {
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entry:
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; 32: t16:
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; 32: calll {{_?}}bar4
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; 32: fstp
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; 64: t16:
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; 64: jmp {{_?}}bar4
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%0 = tail call double @bar4() nounwind
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ret void
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}
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declare double @bar4()
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; rdar://6283267
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define void @t17() nounwind ssp {
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entry:
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; 32: t17:
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; 32: jmp {{_?}}bar5
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; 64: t17:
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; 64: xorb %al, %al
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; 64: jmp {{_?}}bar5
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tail call void (...)* @bar5() nounwind
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ret void
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}
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declare void @bar5(...)
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; rdar://7774847
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define void @t18() nounwind ssp {
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entry:
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; 32: t18:
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; 32: calll {{_?}}bar6
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; 32: fstp %st(0)
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; 64: t18:
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; 64: xorb %al, %al
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; 64: jmp {{_?}}bar6
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%0 = tail call double (...)* @bar6() nounwind
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ret void
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}
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declare double @bar6(...)
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define void @t19() alignstack(32) nounwind {
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entry:
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; CHECK: t19:
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; CHECK: andl $-32
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; CHECK: calll {{_?}}foo
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tail call void @foo() nounwind
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ret void
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}
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; If caller / callee calling convention mismatch then check if the return
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; values are returned in the same registers.
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; rdar://7874780
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define double @t20(double %x) nounwind {
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entry:
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; 32: t20:
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; 32: calll {{_?}}foo20
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; 32: fldl (%esp)
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; 64: t20:
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; 64: jmp {{_?}}foo20
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%0 = tail call fastcc double @foo20(double %x) nounwind
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ret double %0
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}
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declare fastcc double @foo20(double) nounwind
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