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1feb5854ae
Track new virtual registers by register number, rather than by the live interval created for them. This is the first step in separating the creation of new virtual registers and new live intervals. Eventually live intervals will be created and populated on demand after the virtual registers have been created and used in instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188434 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
8.3 KiB
C++
218 lines
8.3 KiB
C++
//===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//
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// The parent register is never changed. Instead, a number of new virtual
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// registers are created and added to the newRegs vector.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
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#define LLVM_CODEGEN_LIVERANGEEDIT_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AliasAnalysis;
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class LiveIntervals;
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class MachineBlockFrequencyInfo;
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class MachineLoopInfo;
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class VirtRegMap;
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class LiveRangeEdit {
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public:
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/// Callback methods for LiveRangeEdit owners.
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class Delegate {
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virtual void anchor();
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public:
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/// Called immediately before erasing a dead machine instruction.
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virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
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/// Called when a virtual register is no longer used. Return false to defer
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/// its deletion from LiveIntervals.
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virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
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/// Called before shrinking the live range of a virtual register.
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virtual void LRE_WillShrinkVirtReg(unsigned) {}
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/// Called after cloning a virtual register.
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/// This is used for new registers representing connected components of Old.
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virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
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virtual ~Delegate() {}
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};
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private:
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LiveInterval *Parent;
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SmallVectorImpl<unsigned> &NewRegs;
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MachineRegisterInfo &MRI;
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LiveIntervals &LIS;
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VirtRegMap *VRM;
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const TargetInstrInfo &TII;
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Delegate *const TheDelegate;
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/// FirstNew - Index of the first register added to NewRegs.
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const unsigned FirstNew;
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/// ScannedRemattable - true when remattable values have been identified.
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bool ScannedRemattable;
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/// Remattable - Values defined by remattable instructions as identified by
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/// tii.isTriviallyReMaterializable().
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SmallPtrSet<const VNInfo*,4> Remattable;
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/// Rematted - Values that were actually rematted, and so need to have their
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/// live range trimmed or entirely removed.
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SmallPtrSet<const VNInfo*,4> Rematted;
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/// scanRemattable - Identify the Parent values that may rematerialize.
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void scanRemattable(AliasAnalysis *aa);
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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SlotIndex UseIdx) const;
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/// foldAsLoad - If LI has a single use and a single def that can be folded as
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/// a load, eliminate the register by folding the def into the use.
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bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);
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typedef SetVector<LiveInterval*,
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SmallVector<LiveInterval*, 8>,
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SmallPtrSet<LiveInterval*, 8> > ToShrinkSet;
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/// Helper for eliminateDeadDefs.
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void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink);
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public:
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/// Create a LiveRangeEdit for breaking down parent into smaller pieces.
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/// @param parent The register being spilled or split.
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/// @param newRegs List to receive any new registers created. This needn't be
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/// empty initially, any existing registers are ignored.
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/// @param MF The MachineFunction the live range edit is taking place in.
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/// @param lis The collection of all live intervals in this function.
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/// @param vrm Map of virtual registers to physical registers for this
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/// function. If NULL, no virtual register map updates will
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/// be done. This could be the case if called before Regalloc.
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LiveRangeEdit(LiveInterval *parent,
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SmallVectorImpl<unsigned> &newRegs,
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MachineFunction &MF,
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LiveIntervals &lis,
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VirtRegMap *vrm,
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Delegate *delegate = 0)
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: Parent(parent), NewRegs(newRegs),
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MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
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TII(*MF.getTarget().getInstrInfo()),
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TheDelegate(delegate),
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FirstNew(newRegs.size()),
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ScannedRemattable(false) {}
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LiveInterval &getParent() const {
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assert(Parent && "No parent LiveInterval");
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return *Parent;
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}
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unsigned getReg() const { return getParent().reg; }
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/// Iterator for accessing the new registers added by this edit.
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typedef SmallVectorImpl<unsigned>::const_iterator iterator;
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iterator begin() const { return NewRegs.begin()+FirstNew; }
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iterator end() const { return NewRegs.end(); }
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unsigned size() const { return NewRegs.size()-FirstNew; }
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bool empty() const { return size() == 0; }
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unsigned get(unsigned idx) const { return NewRegs[idx+FirstNew]; }
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ArrayRef<unsigned> regs() const {
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return makeArrayRef(NewRegs).slice(FirstNew);
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}
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/// createFrom - Create a new virtual register based on OldReg.
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LiveInterval &createFrom(unsigned OldReg);
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/// create - Create a new register with the same class and original slot as
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/// parent.
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LiveInterval &create() {
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return createFrom(getReg());
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}
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/// anyRematerializable - Return true if any parent values may be
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/// rematerializable.
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/// This function must be called before any rematerialization is attempted.
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bool anyRematerializable(AliasAnalysis*);
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/// checkRematerializable - Manually add VNI to the list of rematerializable
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/// values if DefMI may be rematerializable.
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bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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AliasAnalysis*);
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/// Remat - Information needed to rematerialize at a specific location.
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struct Remat {
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VNInfo *ParentVNI; // parent_'s value at the remat location.
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MachineInstr *OrigMI; // Instruction defining ParentVNI.
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explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
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};
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/// canRematerializeAt - Determine if ParentVNI can be rematerialized at
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/// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
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/// When cheapAsAMove is set, only cheap remats are allowed.
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bool canRematerializeAt(Remat &RM,
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SlotIndex UseIdx,
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bool cheapAsAMove);
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/// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
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/// instruction into MBB before MI. The new instruction is mapped, but
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/// liveness is not updated.
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/// Return the SlotIndex of the new instruction.
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SlotIndex rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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const TargetRegisterInfo&,
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bool Late = false);
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/// markRematerialized - explicitly mark a value as rematerialized after doing
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/// it manually.
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void markRematerialized(const VNInfo *ParentVNI) {
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Rematted.insert(ParentVNI);
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}
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/// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
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bool didRematerialize(const VNInfo *ParentVNI) const {
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return Rematted.count(ParentVNI);
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}
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/// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
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/// to erase it from LIS.
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void eraseVirtReg(unsigned Reg);
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/// eliminateDeadDefs - Try to delete machine instructions that are now dead
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/// (allDefsAreDead returns true). This may cause live intervals to be trimmed
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/// and further dead efs to be eliminated.
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/// RegsBeingSpilled lists registers currently being spilled by the register
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/// allocator. These registers should not be split into new intervals
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/// as currently those new intervals are not guaranteed to spill.
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void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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ArrayRef<unsigned> RegsBeingSpilled = None);
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/// calculateRegClassAndHint - Recompute register class and hint for each new
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/// register.
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void calculateRegClassAndHint(MachineFunction&,
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const MachineLoopInfo&,
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const MachineBlockFrequencyInfo&);
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};
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}
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#endif
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