llvm-6502/test/CodeGen
Sanjoy Das 8fadf8f4d3 [SelectionDAG] Fix PR23603.
Summary:
LLVM's MI level notion of invariant_load is different from LLVM's IR
level notion of invariant_load with respect to dereferenceability.  The
IR notion of invariant_load only guarantees that all *non-faulting*
invariant loads result in the same value.  The MI notion of invariant
load guarantees that the load can be legally moved to any location
within its containing function.  The MI notion of invariant_load is
stronger than the IR notion of invariant_load -- an MI invariant_load is
an IR invariant_load + a guarantee that the location being loaded from
is dereferenceable throughout the function's lifetime.

Reviewers: hfinkel, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238881 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 22:33:30 +00:00
..
AArch64 AArch64: Use CMP;CCMP sequences for and/or/setcc trees. 2015-06-01 22:31:17 +00:00
ARM Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs" 2015-06-02 11:47:30 +00:00
BPF
CPP
Generic Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
Hexagon Revert "[Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath." 2015-06-01 19:20:47 +00:00
Inputs
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR MIR Serialization: use correct line and column numbers for LLVM IR errors. 2015-05-29 17:05:41 +00:00
MSP430
NVPTX [NVPTXFavorNonGenericAddrSpaces] recursively trace into GEP and BitCast 2015-05-29 17:00:27 +00:00
PowerPC Add support for VSX FMA single-precision instructions to the PPC back end 2015-05-29 17:13:25 +00:00
R600 LiveRangeEdit: Fix liveranges not shrinking on subrange kill. 2015-06-01 21:26:26 +00:00
SPARC Add support for the Sparc implementation-defined "ASR" registers. 2015-05-18 16:29:48 +00:00
SystemZ [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load 2015-05-05 19:34:10 +00:00
Thumb Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM. 2015-05-28 20:02:45 +00:00
Thumb2 Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs" 2015-06-02 11:47:30 +00:00
WinEH [WinEH] C++ EH state numbering fixes 2015-05-20 23:22:24 +00:00
X86 [SelectionDAG] Fix PR23603. 2015-06-02 22:33:30 +00:00
XCore