Sean Callanan 201dfa7432 Fixed PALIGNR to take 8-bit rotations in all cases. ...

Also fixed the corresponding testcase, and the PALIGNR
  intrinsic (tested for correctness with llvm-gcc).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89491 91177308-0d34-0410-b5e6-96231b3b80d8

2009-11-20 21:40:28 +00:00

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Alpha

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ARM

Remat VLDRD from constpool. Clean up some instruction property specifications.

2009-11-20 19:57:15 +00:00

Blackfin

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CBackend

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CellSPU

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CPP

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Generic

Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048),

2009-11-20 10:45:10 +00:00

Mips

Unbreak test, Bruno please check.

2009-11-19 07:18:49 +00:00

MSP430

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PIC16

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PowerPC

Check if subreg index is zero.

2009-11-16 06:31:49 +00:00

SPARC

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SystemZ

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Thumb

More consistent thumb1 asm printing.

2009-11-19 06:57:41 +00:00

Thumb2

Remat VLDRD from constpool. Clean up some instruction property specifications.

2009-11-20 19:57:15 +00:00

X86

Fixed PALIGNR to take 8-bit rotations in all cases.

2009-11-20 21:40:28 +00:00

XCore

Add XCore support for indirectbr / blockaddress.

2009-11-18 23:20:42 +00:00