llvm-6502/test/CodeGen/Thumb2/v8_IT_5.ll
Weiming Zhao 929bdb2379 Enable generating legacy IT block for AArch32
By default, the behavior of IT block generation will be determinated
dynamically base on the arch (armv8 vs armv7). This patch adds backend
options: -arm-restrict-it and -arm-no-restrict-it.  The former one
restricts the generation of IT blocks (the same behavior as thumbv8) for
both arches. The later one allows the generation of legacy IT block (the
same behavior as ARMv7 Thumb2) for both arches.

Clang will support -mrestrict-it and -mno-restrict-it, which is
compatible with GCC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 18:29:49 +00:00

64 lines
1.2 KiB
LLVM

; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck %s
; CHECK: it ne
; CHECK-NEXT: cmpne
; CHECK-NEXT: beq
; CHECK: cmp
; CHECK-NEXT: beq
; CHECK-NEXT: %if.else163
; CHECK-NEXT: mov.w
; CHECK-NEXT: b
; CHECK-NEXT: %if.else145
; CHECK-NEXT: mov.w
%struct.hc = type { i32, i32, i32, i32 }
define i32 @t(i32 %type) optsize {
entry:
br i1 undef, label %if.then, label %if.else
if.then:
unreachable
if.else:
br i1 undef, label %if.then15, label %if.else18
if.then15:
unreachable
if.else18:
switch i32 %type, label %if.else173 [
i32 3, label %if.then115
i32 1, label %if.then102
]
if.then102:
br i1 undef, label %cond.true10.i, label %t.exit
cond.true10.i:
br label %t.exit
t.exit:
unreachable
if.then115:
br i1 undef, label %if.else163, label %if.else145
if.else145:
%call150 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34865152) optsize
br label %while.body172
if.else163:
%call168 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34078720) optsize
br label %while.body172
while.body172:
br label %while.body172
if.else173:
ret i32 -1
}
declare hidden fastcc %struct.hc* @foo(%struct.hc* nocapture, i32) nounwind optsize