Colin LeMahieu 20856353b8 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223821 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-09 20:23:30 +00:00
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alu32_alu.txt	[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.	2014-12-09 20:23:30 +00:00
alu32_perm.txt	[Hexagon] Adding combine reg, reg with predicated forms.	2014-12-08 17:33:06 +00:00
alu32_pred.txt	[Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.	2014-12-09 20:23:30 +00:00
cr.txt	[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.	2014-12-08 23:07:59 +00:00
lit.local.cfg	[Hexagon] Adding lit exception if Hexagon isn't built.	2014-12-04 04:28:38 +00:00
xtype_alu.txt	[Hexagon] Fixing broken test.	2014-12-08 22:29:06 +00:00
xtype_bit.txt	[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.	2014-12-08 21:19:18 +00:00
xtype_pred.txt	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00