Manman Ren 73c2f7f5ed X86: peephole optimization to remove cmp instruction ... This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8		2012-06-01 19:49:33 +00:00
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ARM	Make this testcase independent of register allocation.	2012-05-31 18:07:02 +00:00
CellSPU
CPP
Generic	Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>	2012-05-30 00:17:12 +00:00
Hexagon
MBlaze
Mips	Add support for the mips inline asm 'm' output modifier.	2012-05-30 19:05:19 +00:00
MSP430	These tests used intrinsics with the wrong prototype. They weren't caught because	2012-05-27 19:35:41 +00:00
NVPTX	Add llvm.fabs intrinsic.	2012-05-28 21:48:37 +00:00
PowerPC
SPARC
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X86	X86: peephole optimization to remove cmp instruction	2012-06-01 19:49:33 +00:00
XCore