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b228657acc
specify aliases directly in register definitions. Patch contributed by Jason Eckhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
3.9 KiB
C++
106 lines
3.9 KiB
C++
//===- SkeletonRegisterInfo.td - Describe the Register File -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target's register file in Tablegen format.
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//
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//===----------------------------------------------------------------------===//
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class SkelReg<string n> : Register<n> {
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let Namespace = "Skeleton";
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}
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// This is roughly the PPC register file. You should replace all of this with
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// whatever your target needs.
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// GPR - One of the 32 32-bit general-purpose registers
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class GPR<bits<5> num, string n> : SkelReg<n> {
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field bits<5> Num = num;
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}
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// SPR - One of the 32-bit special-purpose registers
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class SPR<bits<5> num, string n> : SkelReg<n> {
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field bits<5> Num = num;
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}
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// FPR - One of the 32 64-bit floating-point registers
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class FPR<bits<5> num, string n> : SkelReg<n> {
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field bits<5> Num = num;
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}
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// CR - One of the 8 4-bit condition registers
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class CR<bits<5> num, string n> : SkelReg<n> {
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field bits<5> Num = num;
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}
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// General-purpose registers
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def R0 : GPR< 0, "R0">; def R1 : GPR< 1, "R1">;
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def R2 : GPR< 2, "R2">; def R3 : GPR< 3, "R3">;
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def R4 : GPR< 4, "R4">; def R5 : GPR< 5, "R5">;
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def R6 : GPR< 6, "R6">; def R7 : GPR< 7, "R7">;
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def R8 : GPR< 8, "R8">; def R9 : GPR< 9, "R9">;
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def R10 : GPR<10, "R10">; def R11 : GPR<11, "R11">;
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def R12 : GPR<12, "R12">; def R13 : GPR<13, "R13">;
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def R14 : GPR<14, "R14">; def R15 : GPR<15, "R15">;
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def R16 : GPR<16, "R16">; def R17 : GPR<17, "R17">;
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def R18 : GPR<18, "R18">; def R19 : GPR<19, "R19">;
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def R20 : GPR<20, "R20">; def R21 : GPR<21, "R21">;
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def R22 : GPR<22, "R22">; def R23 : GPR<23, "R23">;
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def R24 : GPR<24, "R24">; def R25 : GPR<25, "R25">;
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def R26 : GPR<26, "R26">; def R27 : GPR<27, "R27">;
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def R28 : GPR<28, "R28">; def R29 : GPR<29, "R29">;
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def R30 : GPR<30, "R30">; def R31 : GPR<31, "R31">;
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// Floating-point registers
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def F0 : FPR< 0, "F0">; def F1 : FPR< 1, "F1">;
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def F2 : FPR< 2, "F2">; def F3 : FPR< 3, "F3">;
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def F4 : FPR< 4, "F4">; def F5 : FPR< 5, "F5">;
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def F6 : FPR< 6, "F6">; def F7 : FPR< 7, "F7">;
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def F8 : FPR< 8, "F8">; def F9 : FPR< 9, "F9">;
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def F10 : FPR<10, "F10">; def F11 : FPR<11, "F11">;
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def F12 : FPR<12, "F12">; def F13 : FPR<13, "F13">;
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def F14 : FPR<14, "F14">; def F15 : FPR<15, "F15">;
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def F16 : FPR<16, "F16">; def F17 : FPR<17, "F17">;
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def F18 : FPR<18, "F18">; def F19 : FPR<19, "F19">;
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def F20 : FPR<20, "F20">; def F21 : FPR<21, "F21">;
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def F22 : FPR<22, "F22">; def F23 : FPR<23, "F23">;
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def F24 : FPR<24, "F24">; def F25 : FPR<25, "F25">;
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def F26 : FPR<26, "F26">; def F27 : FPR<27, "F27">;
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def F28 : FPR<28, "F28">; def F29 : FPR<29, "F29">;
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def F30 : FPR<30, "F30">; def F31 : FPR<31, "F31">;
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// Condition registers
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def CR0 : CR<0, "CR0">; def CR1 : CR<1, "CR1">;
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def CR2 : CR<2, "CR2">; def CR3 : CR<3, "CR3">;
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def CR4 : CR<4, "CR4">; def CR5 : CR<5, "CR5">;
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def CR6 : CR<6, "CR6">; def CR7 : CR<7, "CR7">;
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// Floating-point status and control register
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def FPSCR : SPR<0, "FPSCR">;
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// fiXed-point Exception Register? :-)
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def XER : SPR<1, "XER">;
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// Link register
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def LR : SPR<2, "LR">;
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// Count register
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def CTR : SPR<3, "CTR">;
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// These are the "time base" registers which are read-only in user mode.
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def TBL : SPR<4, "TBL">;
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def TBU : SPR<5, "TBU">;
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/// Register classes: one for floats and another for non-floats.
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///
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def GPRC : RegisterClass<i32, 32, [R0, R1, R2, R3, R4, R5, R6, R7,
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R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
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R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
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def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
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F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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