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https://github.com/c64scene-ar/llvm-6502.git
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49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
973 B
LLVM
56 lines
973 B
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
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; i16
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define i16 @cvt_i16_i32(i32 %x) {
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; CHECK: cvt.u16.u32 %rs{{[0-9]+}}, %r{{[0-9]+}}
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; CHECK: ret
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%a = trunc i32 %x to i16
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ret i16 %a
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}
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define i16 @cvt_i16_i64(i64 %x) {
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; CHECK: cvt.u16.u64 %rs{{[0-9]+}}, %rl{{[0-9]+}}
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; CHECK: ret
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%a = trunc i64 %x to i16
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ret i16 %a
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}
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; i32
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define i32 @cvt_i32_i16(i16 %x) {
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; CHECK: cvt.u32.u16 %r{{[0-9]+}}, %rs{{[0-9]+}}
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; CHECK: ret
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%a = zext i16 %x to i32
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ret i32 %a
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}
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define i32 @cvt_i32_i64(i64 %x) {
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; CHECK: cvt.u32.u64 %r{{[0-9]+}}, %rl{{[0-9]+}}
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; CHECK: ret
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%a = trunc i64 %x to i32
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ret i32 %a
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}
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; i64
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define i64 @cvt_i64_i16(i16 %x) {
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; CHECK: cvt.u64.u16 %rl{{[0-9]+}}, %rs{{[0-9]+}}
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; CHECK: ret
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%a = zext i16 %x to i64
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ret i64 %a
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}
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define i64 @cvt_i64_i32(i32 %x) {
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; CHECK: cvt.u64.u32 %rl{{[0-9]+}}, %r{{[0-9]+}}
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; CHECK: ret
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%a = zext i32 %x to i64
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ret i64 %a
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}
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