mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-11 07:24:06 +00:00
57c3dac0df
and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56825 91177308-0d34-0410-b5e6-96231b3b80d8
433 lines
18 KiB
C++
433 lines
18 KiB
C++
//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "X86.h"
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#include "X86RegisterInfo.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class X86RegisterInfo;
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class X86TargetMachine;
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namespace X86 {
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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COND_INVALID
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};
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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}
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace X86II {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction types. These are the standard/most common forms for X86
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// instructions.
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//
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// Raw - This form is for instructions that don't have any operands, so
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/// they are just a fixed opcode value, like 'leave'.
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RawFrm = 1,
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/// AddRegFrm - This form is used for instructions like 'push r32' that have
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/// their one register operand added to their opcode.
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AddRegFrm = 2,
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/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is a register.
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///
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MRMDestReg = 3,
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/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is memory.
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///
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MRMDestMem = 4,
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/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is a register.
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///
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MRMSrcReg = 5,
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/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is memory.
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///
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MRMSrcMem = 6,
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/// MRM[0-7][rm] - These forms are used to represent instructions that use
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/// a Mod/RM byte, and use the middle field to hold extended opcode
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/// information. In the intel manual these are represented as /0, /1, ...
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///
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// First, instructions that operate on a register r/m operand...
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MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
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MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
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// Next, instructions that operate on a memory r/m operand...
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MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
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MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
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// MRMInitReg - This form is used for instructions whose source and
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// destinations are the same register.
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MRMInitReg = 32,
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FormMask = 63,
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//===------------------------------------------------------------------===//
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// Actual flags...
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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OpSize = 1 << 6,
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// which most often indicates that the instruction address 16 bit address
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// instead of 32 bit address (or 32 bit address in 64 bit mode).
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AdSize = 1 << 7,
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//===------------------------------------------------------------------===//
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
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// used to obtain the setting of this field. If no bits in this field is
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// set, there is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Shift = 8,
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Op0Mask = 0xF << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << Op0Shift,
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// REP - The 0xF3 prefix byte indicating repetition of the following
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// instruction.
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REP = 2 << Op0Shift,
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
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DA = 5 << Op0Shift, DB = 6 << Op0Shift,
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DC = 7 << Op0Shift, DD = 8 << Op0Shift,
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DE = 9 << Op0Shift, DF = 10 << Op0Shift,
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// XS, XD - These prefix codes are for single and double precision scalar
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// floating point operations performed in the SSE registers.
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XD = 11 << Op0Shift, XS = 12 << Op0Shift,
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// T8, TA - Prefix after the 0x0F prefix.
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T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
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//===------------------------------------------------------------------===//
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// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
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// They are used to specify GPRs and SSE registers, 64-bit operand size,
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// etc. We only cares about REX.W and REX.R bits and only the former is
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// statically determined.
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//
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REXShift = 12,
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REX_W = 1 << REXShift,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmShift = 13,
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ImmMask = 7 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm16 = 2 << ImmShift,
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Imm32 = 3 << ImmShift,
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Imm64 = 4 << ImmShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = 16,
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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NotFP = 0 << FPTypeShift,
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << FPTypeShift,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << FPTypeShift,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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//
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OneArgFPRW = 3 << FPTypeShift,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << FPTypeShift,
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// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
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// explicit argument, but have no destination. Example: fucom, fucomi, ...
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CompareFP = 5 << FPTypeShift,
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// CondMovFP - "2 operand" floating point conditional move instructions.
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CondMovFP = 6 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 7 << FPTypeShift,
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// Lock prefix
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LOCKShift = 19,
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LOCK = 1 << LOCKShift,
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// Bits 20 -> 23 are unused
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OpcodeShift = 24,
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OpcodeMask = 0xFF << OpcodeShift
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};
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}
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inline static bool isScale(const MachineOperand &MO) {
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return MO.isImmediate() &&
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(MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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}
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inline static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&
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(MI->getOperand(Op+3).isImmediate() ||
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MI->getOperand(Op+3).isGlobalAddress() ||
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MI->getOperand(Op+3).isConstantPoolIndex() ||
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MI->getOperand(Op+3).isJumpTableIndex());
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}
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class X86InstrInfo : public TargetInstrInfoImpl {
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X86TargetMachine &TM;
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const X86RegisterInfo RI;
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/// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2 - Load / store folding opcode maps.
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///
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
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DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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///
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DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
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public:
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explicit X86InstrInfo(X86TargetMachine &tm);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
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unsigned& destReg) const;
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unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
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unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
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bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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bool isInvariantLoad(MachineInstr *MI) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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// Branch analysis.
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virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const;
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const;
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/// foldMemoryOperand - If this target supports it, fold a load or store of
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/// the specified stack slot into the specified machine instruction for the
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/// specified operand(s). If this is possible, the target should perform the
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/// folding and return true, otherwise it should return false. If it folds
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/// the instruction, it is likely that the MachineInstruction the iterator
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/// references has been changed.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const;
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/// canFoldMemoryOperand - Returns true if the specified load / store is
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/// folding is possible.
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virtual bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const;
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/// unfoldMemoryOperand - Separate a single instruction which folded a load or
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/// a store or a load and a store into two or more instruction. If this is
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/// possible, returns true as well as the new instructions by reference.
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virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const;
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/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
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/// instruction after load / store are unfolded from an instruction of the
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/// specified opcode. It returns zero if the specified unfolding is not
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/// possible.
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virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore) const;
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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const TargetRegisterClass *getPointerRegClass() const;
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified machine instruction.
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//
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unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
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return TID->TSFlags >> X86II::OpcodeShift;
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}
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unsigned char getBaseOpcodeFor(unsigned Opcode) const {
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return getBaseOpcodeFor(&get(Opcode));
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}
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static bool isX86_64NonExtLowByteReg(unsigned reg) {
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return (reg == X86::SPL || reg == X86::BPL ||
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reg == X86::SIL || reg == X86::DIL);
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}
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static unsigned sizeOfImm(const TargetInstrDesc *Desc);
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static unsigned getX86RegNum(unsigned RegNo);
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static bool isX86_64ExtendedReg(const MachineOperand &MO);
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static unsigned determineREX(const MachineInstr &MI);
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned getGlobalBaseReg(MachineFunction *MF) const;
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private:
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MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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unsigned OpNum,
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SmallVector<MachineOperand,4> &MOs) const;
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};
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} // End llvm namespace
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#endif
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