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214c554b64
In MachO for AArch64 it is possible to have an explicit addend defined by the ARM64_RELOC_ADDEND relocation or having an addend encoded within the instruction. Only one of them are allowed per relocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213687 91177308-0d34-0410-b5e6-96231b3b80d8
256 lines
10 KiB
C++
256 lines
10 KiB
C++
//===-- RuntimeDyldMachOAArch64.h -- MachO/AArch64 specific code. -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_RUNTIMEDYLDMACHOAARCH64_H
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#define LLVM_RUNTIMEDYLDMACHOAARCH64_H
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#include "../RuntimeDyldMachO.h"
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#define DEBUG_TYPE "dyld"
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namespace llvm {
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class RuntimeDyldMachOAArch64
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: public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOAArch64> {
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public:
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RuntimeDyldMachOAArch64(RTDyldMemoryManager *MM)
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: RuntimeDyldMachOCRTPBase(MM) {}
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unsigned getMaxStubSize() override { return 8; }
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unsigned getStubAlignment() override { return 8; }
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relocation_iterator
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processRelocationRef(unsigned SectionID, relocation_iterator RelI,
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ObjectImage &ObjImg, ObjSectionToIDMap &ObjSectionToID,
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const SymbolTableMap &Symbols, StubMap &Stubs) override {
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const MachOObjectFile &Obj =
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static_cast<const MachOObjectFile &>(*ObjImg.getObjectFile());
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MachO::any_relocation_info RelInfo =
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Obj.getRelocation(RelI->getRawDataRefImpl());
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assert(!Obj.isRelocationScattered(RelInfo) && "");
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// ARM64 has an ARM64_RELOC_ADDEND relocation type that carries an explicit
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// addend for the following relocation. If found: (1) store the associated
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// addend, (2) consume the next relocation, and (3) use the stored addend to
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// override the addend.
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int64_t ExplicitAddend = 0;
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if (Obj.getAnyRelocationType(RelInfo) == MachO::ARM64_RELOC_ADDEND) {
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assert(!Obj.getPlainRelocationExternal(RelInfo));
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assert(!Obj.getAnyRelocationPCRel(RelInfo));
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assert(Obj.getAnyRelocationLength(RelInfo) == 2);
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int64_t RawAddend = Obj.getPlainRelocationSymbolNum(RelInfo);
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// Sign-extend the 24-bit to 64-bit.
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ExplicitAddend = SignExtend64(RawAddend, 24);
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++RelI;
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RelInfo = Obj.getRelocation(RelI->getRawDataRefImpl());
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}
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RelocationEntry RE(getBasicRelocationEntry(SectionID, ObjImg, RelI));
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RelocationValueRef Value(
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getRelocationValueRef(ObjImg, RelI, RE, ObjSectionToID, Symbols));
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assert((ExplicitAddend == 0 || RE.Addend == 0) && "Relocation has "\
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"ARM64_RELOC_ADDEND and embedded addend in the instruction.");
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if (ExplicitAddend) {
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RE.Addend = ExplicitAddend;
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Value.Addend = ExplicitAddend;
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}
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bool IsExtern = Obj.getPlainRelocationExternal(RelInfo);
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if (!IsExtern && RE.IsPCRel)
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makeValueAddendPCRel(Value, ObjImg, RelI);
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RE.Addend = Value.Addend;
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if (RE.RelType == MachO::ARM64_RELOC_GOT_LOAD_PAGE21 ||
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RE.RelType == MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12)
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processGOTRelocation(RE, Value, Stubs);
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else {
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if (Value.SymbolName)
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addRelocationForSymbol(RE, Value.SymbolName);
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else
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addRelocationForSection(RE, Value.SectionID);
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}
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return ++RelI;
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}
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void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
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DEBUG(dumpRelocationToResolve(RE, Value));
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const SectionEntry &Section = Sections[RE.SectionID];
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uint8_t *LocalAddress = Section.Address + RE.Offset;
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switch (RE.RelType) {
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default:
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llvm_unreachable("Invalid relocation type!");
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case MachO::ARM64_RELOC_UNSIGNED: {
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assert(!RE.IsPCRel && "PCRel and ARM64_RELOC_UNSIGNED not supported");
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// Mask in the target value a byte at a time (we don't have an alignment
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// guarantee for the target address, so this is safest).
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if (RE.Size < 2)
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llvm_unreachable("Invalid size for ARM64_RELOC_UNSIGNED");
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writeBytesUnaligned(LocalAddress, Value + RE.Addend, 1 << RE.Size);
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break;
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}
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case MachO::ARM64_RELOC_BRANCH26: {
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assert(RE.IsPCRel && "not PCRel and ARM64_RELOC_BRANCH26 not supported");
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// Mask the value into the target address. We know instructions are
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// 32-bit aligned, so we can do it all at once.
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uint32_t *p = (uint32_t *)LocalAddress;
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// Check if the addend is encoded in the instruction.
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uint32_t EncodedAddend = *p & 0x03FFFFFF;
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if (EncodedAddend != 0) {
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if (RE.Addend == 0)
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llvm_unreachable("branch26 instruction has embedded addend.");
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else
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llvm_unreachable("branch26 instruction has embedded addend and"
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"ARM64_RELOC_ADDEND.");
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}
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// Check if branch is in range.
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uint64_t FinalAddress = Section.LoadAddress + RE.Offset;
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uint64_t PCRelVal = Value - FinalAddress + RE.Addend;
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assert(isInt<26>(PCRelVal) && "Branch target out of range!");
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// Insert the value into the instruction.
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*p = (*p & 0xFC000000) | ((uint32_t)(PCRelVal >> 2) & 0x03FFFFFF);
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break;
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}
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case MachO::ARM64_RELOC_GOT_LOAD_PAGE21:
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case MachO::ARM64_RELOC_PAGE21: {
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assert(RE.IsPCRel && "not PCRel and ARM64_RELOC_PAGE21 not supported");
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// Mask the value into the target address. We know instructions are
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// 32-bit aligned, so we can do it all at once.
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uint32_t *p = (uint32_t *)LocalAddress;
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// Check if the addend is encoded in the instruction.
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uint32_t EncodedAddend =
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((*p & 0x60000000) >> 29) | ((*p & 0x01FFFFE0) >> 3);
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if (EncodedAddend != 0) {
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if (RE.Addend == 0)
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llvm_unreachable("adrp instruction has embedded addend.");
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else
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llvm_unreachable("adrp instruction has embedded addend and"
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"ARM64_RELOC_ADDEND.");
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}
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// Adjust for PC-relative relocation and offset.
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uint64_t FinalAddress = Section.LoadAddress + RE.Offset;
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uint64_t PCRelVal =
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((Value + RE.Addend) & (-4096)) - (FinalAddress & (-4096));
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// Check that the value fits into 21 bits (+ 12 lower bits).
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assert(isInt<33>(PCRelVal) && "Invalid page reloc value!");
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// Insert the value into the instruction.
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uint32_t ImmLoValue = (uint32_t)(PCRelVal << 17) & 0x60000000;
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uint32_t ImmHiValue = (uint32_t)(PCRelVal >> 9) & 0x00FFFFE0;
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*p = (*p & 0x9F00001F) | ImmHiValue | ImmLoValue;
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break;
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}
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case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12:
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case MachO::ARM64_RELOC_PAGEOFF12: {
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assert(!RE.IsPCRel && "PCRel and ARM64_RELOC_PAGEOFF21 not supported");
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// Mask the value into the target address. We know instructions are
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// 32-bit aligned, so we can do it all at once.
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uint32_t *p = (uint32_t *)LocalAddress;
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// Check if the addend is encoded in the instruction.
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uint32_t EncodedAddend = *p & 0x003FFC00;
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if (EncodedAddend != 0) {
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if (RE.Addend == 0)
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llvm_unreachable("adrp instruction has embedded addend.");
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else
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llvm_unreachable("adrp instruction has embedded addend and"
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"ARM64_RELOC_ADDEND.");
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}
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// Add the offset from the symbol.
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Value += RE.Addend;
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// Mask out the page address and only use the lower 12 bits.
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Value &= 0xFFF;
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// Check which instruction we are updating to obtain the implicit shift
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// factor from LDR/STR instructions.
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if (*p & 0x08000000) {
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uint32_t ImplicitShift = ((*p >> 30) & 0x3);
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switch (ImplicitShift) {
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case 0:
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// Check if this a vector op.
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if ((*p & 0x04800000) == 0x04800000) {
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ImplicitShift = 4;
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assert(((Value & 0xF) == 0) &&
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"128-bit LDR/STR not 16-byte aligned.");
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}
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break;
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case 1:
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assert(((Value & 0x1) == 0) && "16-bit LDR/STR not 2-byte aligned.");
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case 2:
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assert(((Value & 0x3) == 0) && "32-bit LDR/STR not 4-byte aligned.");
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case 3:
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assert(((Value & 0x7) == 0) && "64-bit LDR/STR not 8-byte aligned.");
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}
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// Compensate for implicit shift.
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Value >>= ImplicitShift;
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}
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// Insert the value into the instruction.
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*p = (*p & 0xFFC003FF) | ((uint32_t)(Value << 10) & 0x003FFC00);
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break;
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}
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case MachO::ARM64_RELOC_SUBTRACTOR:
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case MachO::ARM64_RELOC_POINTER_TO_GOT:
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case MachO::ARM64_RELOC_TLVP_LOAD_PAGE21:
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case MachO::ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
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llvm_unreachable("Relocation type not implemented yet!");
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case MachO::ARM64_RELOC_ADDEND:
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llvm_unreachable("ARM64_RELOC_ADDEND should have been handeled by "
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"processRelocationRef!");
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}
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}
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void finalizeSection(ObjectImage &ObjImg, unsigned SectionID,
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const SectionRef &Section) {}
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private:
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void processGOTRelocation(const RelocationEntry &RE,
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RelocationValueRef &Value, StubMap &Stubs) {
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assert(RE.Size == 2);
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SectionEntry &Section = Sections[RE.SectionID];
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StubMap::const_iterator i = Stubs.find(Value);
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uint8_t *Addr;
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if (i != Stubs.end())
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Addr = Section.Address + i->second;
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else {
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// FIXME: There must be a better way to do this then to check and fix the
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// alignment every time!!!
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uintptr_t BaseAddress = uintptr_t(Section.Address);
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uintptr_t StubAlignment = getStubAlignment();
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uintptr_t StubAddress =
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(BaseAddress + Section.StubOffset + StubAlignment - 1) &
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-StubAlignment;
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unsigned StubOffset = StubAddress - BaseAddress;
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Stubs[Value] = StubOffset;
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assert(((StubAddress % getStubAlignment()) == 0) &&
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"GOT entry not aligned");
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RelocationEntry GOTRE(RE.SectionID, StubOffset,
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MachO::ARM64_RELOC_UNSIGNED, Value.Addend,
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/*IsPCRel=*/false, /*Size=*/3);
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if (Value.SymbolName)
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addRelocationForSymbol(GOTRE, Value.SymbolName);
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else
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addRelocationForSection(GOTRE, Value.SectionID);
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Section.StubOffset = StubOffset + getMaxStubSize();
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Addr = (uint8_t *)StubAddress;
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}
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RelocationEntry TargetRE(RE.SectionID, RE.Offset, RE.RelType, /*Addend=*/0,
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RE.IsPCRel, RE.Size);
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resolveRelocation(TargetRE, (uint64_t)Addr);
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}
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};
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}
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#undef DEBUG_TYPE
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#endif // LLVM_RUNTIMEDYLDMACHOAARCH64_H
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