Venkatraman Govindaraju 21886a495a [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. ... Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-19 20:07:20 +00:00
..
AArch64	More test coverage for addFrameMove.	2013-05-16 20:50:56 +00:00
ARM	Support unaligned load/store on more ARM targets	2013-05-17 23:49:01 +00:00
CPP
Generic	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze
Mips	[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).	2013-05-16 21:17:15 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.	2013-03-30 14:29:30 +00:00
PowerPC	Check InlineAsm clobbers in PPCCTRLoops	2013-05-18 09:20:39 +00:00
R600	R600: Lower int_load_input to copyFromReg instead of Register node	2013-05-17 16:51:06 +00:00
SI
SPARC	[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.	2013-05-19 20:07:20 +00:00
SystemZ	[SystemZ] Make use of SUBTRACT HALFWORD	2013-05-15 15:05:29 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	X86: Bad peephole interaction between adc, MOV32r0	2013-05-18 01:02:03 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00