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https://github.com/c64scene-ar/llvm-6502.git
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f4c3a5601a
Add implementations of: bool isLegalICmpImmediate(int64_t Imm) const bool isLegalAddImmediate(int64_t Imm) const bool isTruncateFree(Type *Ty1, Type *Ty2) const bool isTruncateFree(EVT VT1, EVT VT2) const bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const Unfortunately, this regresses counter-register-based loop formation because some of the loops now end up in forms were SE cannot compute loop counts. However, nevertheless, the test-suite results favor committing: SingleSource/Benchmarks/BenchmarkGame/puzzle: 26% speedup MultiSource/Benchmarks/FreeBench/analyzer/analyzer: 21% speedup MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan: 20% speedup SingleSource/Benchmarks/Polybench/linear-algebra/kernels/trisolv/trisolv: 19% speedup SingleSource/Benchmarks/Polybench/linear-algebra/kernels/gesummv/gesummv: 15% speedup MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2: 2% speedup MultiSource/Benchmarks/VersaBench/bmm/bmm: 26% slowdown git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206120 91177308-0d34-0410-b5e6-96231b3b80d8
55 lines
1.7 KiB
LLVM
55 lines
1.7 KiB
LLVM
; RUN: llc -O1 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
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; RUN: llvm-readobj -r | FileCheck %s
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; FIXME: When asm-parse is available, could make this an assembly test.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@test_fn_static.si = internal global i32 0, align 4
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define signext i32 @test_fn_static() nounwind {
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entry:
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%0 = load i32* @test_fn_static.si, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @test_fn_static.si, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
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; accessing function-scoped variable si.
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;
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; CHECK: Relocations [
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; CHECK: Section (2) .rela.text {
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
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@gi = global i32 5, align 4
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define signext i32 @test_file_static() nounwind {
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entry:
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%0 = load i32* @gi, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @gi, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
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; accessing file-scope variable gi.
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;
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
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define double @test_double_const() nounwind {
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entry:
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ret double 0x3F4FD4920B498CF0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
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; accessing a constant.
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;
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
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; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
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