mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b625f2f896
and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
1143 lines
44 KiB
C++
1143 lines
44 KiB
C++
//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for PowerPC,
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// converting from a legalized dag to a PPC dag.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ppc-codegen"
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#include "PPC.h"
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#include "PPCPredicates.h"
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#include "PPCTargetMachine.h"
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#include "PPCISelLowering.h"
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#include "PPCHazardRecognizers.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Compiler.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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namespace {
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//===--------------------------------------------------------------------===//
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/// PPCDAGToDAGISel - PPC specific code to select PPC machine
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/// instructions for SelectionDAG operations.
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///
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class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
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PPCTargetMachine &TM;
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PPCTargetLowering PPCLowering;
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const PPCSubtarget &PPCSubTarget;
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unsigned GlobalBaseReg;
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public:
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PPCDAGToDAGISel(PPCTargetMachine &tm)
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: SelectionDAGISel(PPCLowering), TM(tm),
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PPCLowering(*TM.getTargetLowering()),
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PPCSubTarget(*TM.getSubtargetImpl()) {}
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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SelectionDAGISel::runOnFunction(Fn);
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InsertVRSaveCode(Fn);
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return true;
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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/// getSmallIPtrImm - Return a target constant of pointer type.
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inline SDOperand getSmallIPtrImm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
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}
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/// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
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/// with any number of 0s on either side. The 1s are allowed to wrap from
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/// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
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/// 0x0F0F0000 is not, since all 1s are not contiguous.
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static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
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/// isRotateAndMask - Returns true if Mask and Shift can be folded into a
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/// rotate and mask opcode and mask operation.
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static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
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unsigned &SH, unsigned &MB, unsigned &ME);
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
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SDNode *getGlobalBaseReg();
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDNode *Select(SDOperand Op);
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SDNode *SelectBitfieldInsert(SDNode *N);
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/// SelectCC - Select a comparison of the specified values with the
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/// specified condition code, returning the CR# of the expression.
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SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
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/// SelectAddrImm - Returns true if the address N can be represented by
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/// a base register plus a signed 16-bit displacement [r+imm].
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bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
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SDOperand &Base) {
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return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
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}
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/// SelectAddrImmOffs - Return true if the operand is valid for a preinc
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/// immediate field. Because preinc imms have already been validated, just
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/// accept it.
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bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
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Out = N;
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return true;
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}
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/// SelectAddrIdx - Given the specified addressed, check to see if it can be
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/// represented as an indexed [r+r] operation. Returns false if it can
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/// be represented by [r+imm], which are preferred.
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bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
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}
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/// SelectAddrIdxOnly - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation.
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bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
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}
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/// SelectAddrImmShift - Returns true if the address N can be represented by
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/// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
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/// for use by STD and friends.
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bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
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SDOperand &Base) {
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return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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SDOperand Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectAddrIdx(Op, Op, Op0, Op1))
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SelectAddrImm(Op, Op, Op0, Op1);
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break;
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case 'o': // offsetable
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if (!SelectAddrImm(Op, Op, Op0, Op1)) {
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Op0 = Op;
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AddToISelQueue(Op0); // r+0.
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Op1 = getSmallIPtrImm(0);
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}
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break;
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case 'v': // not offsetable
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SelectAddrIdxOnly(Op, Op, Op0, Op1);
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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SDOperand BuildSDIVSequence(SDNode *N);
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SDOperand BuildUDIVSequence(SDNode *N);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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void InsertVRSaveCode(Function &Fn);
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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virtual HazardRecognizer *CreateTargetHazardRecognizer() {
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// Should use subtarget info to pick the right hazard recognizer. For
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// now, always return a PPC970 recognizer.
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const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
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assert(II && "No InstrInfo?");
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return new PPCHazardRecognizer970(*II);
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}
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// Include the pieces autogenerated from the target description.
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#include "PPCGenDAGISel.inc"
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private:
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SDNode *SelectSETCC(SDOperand Op);
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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/// InsertVRSaveCode - Once the entire function has been instruction selected,
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/// all virtual registers are created and all machine instructions are built,
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/// check to see if we need to save/restore VRSAVE. If so, do it.
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void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
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// Check to see if this function uses vector registers, which means we have to
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// save and restore the VRSAVE register and update it with the regs we use.
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//
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// In this case, there will be virtual registers of vector type type created
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// by the scheduler. Detect them now.
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MachineFunction &Fn = MachineFunction::get(&F);
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bool HasVectorVReg = false;
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = RegInfo->getLastVirtReg()+1; i != e; ++i)
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if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
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HasVectorVReg = true;
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break;
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}
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if (!HasVectorVReg) return; // nothing to do.
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// If we have a vector register, we want to emit code into the entry and exit
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// blocks to save and restore the VRSAVE register. We do this here (instead
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// of marking all vector instructions as clobbering VRSAVE) for two reasons:
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//
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// 1. This (trivially) reduces the load on the register allocator, by not
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// having to represent the live range of the VRSAVE register.
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// 2. This (more significantly) allows us to create a temporary virtual
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// register to hold the saved VRSAVE value, allowing this temporary to be
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// register allocated, instead of forcing it to be spilled to the stack.
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// Create two vregs - one to hold the VRSAVE register that is live-in to the
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// function and one for the value after having bits or'd into it.
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unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
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unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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MachineBasicBlock &EntryBB = *Fn.begin();
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// Emit the following code into the entry block:
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// InVRSAVE = MFVRSAVE
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// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
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// MTVRSAVE UpdatedVRSAVE
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MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
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BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
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BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
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UpdatedVRSAVE).addReg(InVRSAVE);
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BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
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// Find all return blocks, outputting a restore in each epilog.
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for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
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if (!BB->empty() && BB->back().getDesc().isReturn()) {
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IP = BB->end(); --IP;
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// Skip over all terminator instructions, which are part of the return
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// sequence.
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MachineBasicBlock::iterator I2 = IP;
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while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
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IP = I2;
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// Emit: MTVRSAVE InVRSave
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BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
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}
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}
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// base address to use for accessing globals into a register.
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///
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SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
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if (!GlobalBaseReg) {
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = BB->getParent()->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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if (PPCLowering.getPointerTy() == MVT::i32) {
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GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
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BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
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BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
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} else {
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GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
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BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
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BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
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}
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}
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return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
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}
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/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// sign extension from a 16-bit value. If so, this returns true and the
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/// immediate.
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static bool isIntS16Immediate(SDNode *N, short &Imm) {
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if (N->getOpcode() != ISD::Constant)
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return false;
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Imm = (short)cast<ConstantSDNode>(N)->getValue();
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if (N->getValueType(0) == MVT::i32)
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return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
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else
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return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
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}
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static bool isIntS16Immediate(SDOperand Op, short &Imm) {
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return isIntS16Immediate(Op.Val, Imm);
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}
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/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
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/// operand. If so Imm will receive the 32-bit value.
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static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
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if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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/// isInt64Immediate - This method tests to see if the node is a 64-bit constant
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/// operand. If so Imm will receive the 64-bit value.
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static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
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if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
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Imm = cast<ConstantSDNode>(N)->getValue();
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return true;
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}
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return false;
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}
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// isInt32Immediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
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return isInt32Immediate(N.Val, Imm);
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}
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// isOpcWithIntImmediate - This method tests to see if the node is a specific
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// opcode and that it has a immediate integer right operand.
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// If so Imm will receive the 32 bit value.
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static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
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return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
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}
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bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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if (isShiftedMask_32(Val)) {
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// look for the first non-zero bit
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MB = CountLeadingZeros_32(Val);
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// look for the first zero bit after the run of ones
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ME = CountLeadingZeros_32((Val - 1) ^ Val);
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return true;
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} else {
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Val = ~Val; // invert mask
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if (isShiftedMask_32(Val)) {
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// effectively look for the first zero bit
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ME = CountLeadingZeros_32(Val) - 1;
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// effectively look for the first one bit after the run of zeros
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MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
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return true;
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}
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}
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// no run present
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return false;
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}
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bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
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bool IsShiftMask, unsigned &SH,
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unsigned &MB, unsigned &ME) {
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// Don't even go down this path for i64, since different logic will be
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// necessary for rldicl/rldicr/rldimi.
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if (N->getValueType(0) != MVT::i32)
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return false;
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unsigned Shift = 32;
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unsigned Indeterminant = ~0; // bit mask marking indeterminant results
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unsigned Opcode = N->getOpcode();
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if (N->getNumOperands() != 2 ||
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!isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
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return false;
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if (Opcode == ISD::SHL) {
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// apply shift left to mask if it comes first
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if (IsShiftMask) Mask = Mask << Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu << Shift);
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} else if (Opcode == ISD::SRL) {
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// apply shift right to mask if it comes first
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if (IsShiftMask) Mask = Mask >> Shift;
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// determine which bits are made indeterminant by shift
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Indeterminant = ~(0xFFFFFFFFu >> Shift);
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// adjust for the left rotate
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Shift = 32 - Shift;
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} else if (Opcode == ISD::ROTL) {
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Indeterminant = 0;
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} else {
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return false;
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}
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// if the mask doesn't intersect any Indeterminant bits
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if (Mask && !(Mask & Indeterminant)) {
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SH = Shift & 31;
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// make sure the mask is still a mask (wrap arounds may not be)
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return isRunOfOnes(Mask, MB, ME);
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}
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return false;
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}
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/// SelectBitfieldInsert - turn an or of two masked values into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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SDOperand Op0 = N->getOperand(0);
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SDOperand Op1 = N->getOperand(1);
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uint64_t LKZ, LKO, RKZ, RKO;
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CurDAG->ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
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CurDAG->ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
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unsigned TargetMask = LKZ;
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unsigned InsertMask = RKZ;
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if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
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unsigned Op0Opc = Op0.getOpcode();
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unsigned Op1Opc = Op1.getOpcode();
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unsigned Value, SH = 0;
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TargetMask = ~TargetMask;
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InsertMask = ~InsertMask;
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// If the LHS has a foldable shift and the RHS does not, then swap it to the
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// RHS so that we can fold the shift into the insert.
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if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
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|
if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
|
|
Op0.getOperand(0).getOpcode() == ISD::SRL) {
|
|
if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
|
|
Op1.getOperand(0).getOpcode() != ISD::SRL) {
|
|
std::swap(Op0, Op1);
|
|
std::swap(Op0Opc, Op1Opc);
|
|
std::swap(TargetMask, InsertMask);
|
|
}
|
|
}
|
|
} else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
|
|
if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
|
|
Op1.getOperand(0).getOpcode() != ISD::SRL) {
|
|
std::swap(Op0, Op1);
|
|
std::swap(Op0Opc, Op1Opc);
|
|
std::swap(TargetMask, InsertMask);
|
|
}
|
|
}
|
|
|
|
unsigned MB, ME;
|
|
if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
|
|
SDOperand Tmp1, Tmp2, Tmp3;
|
|
bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
|
|
|
|
if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
|
|
isInt32Immediate(Op1.getOperand(1), Value)) {
|
|
Op1 = Op1.getOperand(0);
|
|
SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
|
|
}
|
|
if (Op1Opc == ISD::AND) {
|
|
unsigned SHOpc = Op1.getOperand(0).getOpcode();
|
|
if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
|
|
isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
|
|
Op1 = Op1.getOperand(0).getOperand(0);
|
|
SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
|
|
} else {
|
|
Op1 = Op1.getOperand(0);
|
|
}
|
|
}
|
|
|
|
Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
|
|
AddToISelQueue(Tmp3);
|
|
AddToISelQueue(Op1);
|
|
SH &= 31;
|
|
SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
|
|
getI32Imm(ME) };
|
|
return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/// SelectCC - Select a comparison of the specified values with the specified
|
|
/// condition code, returning the CR# of the expression.
|
|
SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
|
|
ISD::CondCode CC) {
|
|
// Always select the LHS.
|
|
AddToISelQueue(LHS);
|
|
unsigned Opc;
|
|
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
unsigned Imm;
|
|
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
|
|
if (isInt32Immediate(RHS, Imm)) {
|
|
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
|
|
if (isUInt16(Imm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
|
|
getI32Imm(Imm & 0xFFFF)), 0);
|
|
// If this is a 16-bit signed immediate, fold it.
|
|
if (isInt16((int)Imm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
|
|
getI32Imm(Imm & 0xFFFF)), 0);
|
|
|
|
// For non-equality comparisons, the default code would materialize the
|
|
// constant, then compare against it, like this:
|
|
// lis r2, 4660
|
|
// ori r2, r2, 22136
|
|
// cmpw cr0, r3, r2
|
|
// Since we are just comparing for equality, we can emit this instead:
|
|
// xoris r0,r3,0x1234
|
|
// cmplwi cr0,r0,0x5678
|
|
// beq cr0,L6
|
|
SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
|
|
getI32Imm(Imm >> 16)), 0);
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
|
|
getI32Imm(Imm & 0xFFFF)), 0);
|
|
}
|
|
Opc = PPC::CMPLW;
|
|
} else if (ISD::isUnsignedIntSetCC(CC)) {
|
|
if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
|
|
getI32Imm(Imm & 0xFFFF)), 0);
|
|
Opc = PPC::CMPLW;
|
|
} else {
|
|
short SImm;
|
|
if (isIntS16Immediate(RHS, SImm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
|
|
getI32Imm((int)SImm & 0xFFFF)),
|
|
0);
|
|
Opc = PPC::CMPW;
|
|
}
|
|
} else if (LHS.getValueType() == MVT::i64) {
|
|
uint64_t Imm;
|
|
if (CC == ISD::SETEQ || CC == ISD::SETNE) {
|
|
if (isInt64Immediate(RHS.Val, Imm)) {
|
|
// SETEQ/SETNE comparison with 16-bit immediate, fold it.
|
|
if (isUInt16(Imm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
|
|
getI32Imm(Imm & 0xFFFF)), 0);
|
|
// If this is a 16-bit signed immediate, fold it.
|
|
if (isInt16(Imm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
|
|
getI32Imm(Imm & 0xFFFF)), 0);
|
|
|
|
// For non-equality comparisons, the default code would materialize the
|
|
// constant, then compare against it, like this:
|
|
// lis r2, 4660
|
|
// ori r2, r2, 22136
|
|
// cmpd cr0, r3, r2
|
|
// Since we are just comparing for equality, we can emit this instead:
|
|
// xoris r0,r3,0x1234
|
|
// cmpldi cr0,r0,0x5678
|
|
// beq cr0,L6
|
|
if (isUInt32(Imm)) {
|
|
SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
|
|
getI64Imm(Imm >> 16)), 0);
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
|
|
getI64Imm(Imm & 0xFFFF)), 0);
|
|
}
|
|
}
|
|
Opc = PPC::CMPLD;
|
|
} else if (ISD::isUnsignedIntSetCC(CC)) {
|
|
if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
|
|
getI64Imm(Imm & 0xFFFF)), 0);
|
|
Opc = PPC::CMPLD;
|
|
} else {
|
|
short SImm;
|
|
if (isIntS16Immediate(RHS, SImm))
|
|
return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
|
|
getI64Imm(SImm & 0xFFFF)),
|
|
0);
|
|
Opc = PPC::CMPD;
|
|
}
|
|
} else if (LHS.getValueType() == MVT::f32) {
|
|
Opc = PPC::FCMPUS;
|
|
} else {
|
|
assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
|
|
Opc = PPC::FCMPUD;
|
|
}
|
|
AddToISelQueue(RHS);
|
|
return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
|
|
}
|
|
|
|
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
|
|
switch (CC) {
|
|
default: assert(0 && "Unknown condition!"); abort();
|
|
case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
|
|
case ISD::SETUEQ:
|
|
case ISD::SETEQ: return PPC::PRED_EQ;
|
|
case ISD::SETONE: // FIXME: This is incorrect see PR642.
|
|
case ISD::SETUNE:
|
|
case ISD::SETNE: return PPC::PRED_NE;
|
|
case ISD::SETOLT: // FIXME: This is incorrect see PR642.
|
|
case ISD::SETULT:
|
|
case ISD::SETLT: return PPC::PRED_LT;
|
|
case ISD::SETOLE: // FIXME: This is incorrect see PR642.
|
|
case ISD::SETULE:
|
|
case ISD::SETLE: return PPC::PRED_LE;
|
|
case ISD::SETOGT: // FIXME: This is incorrect see PR642.
|
|
case ISD::SETUGT:
|
|
case ISD::SETGT: return PPC::PRED_GT;
|
|
case ISD::SETOGE: // FIXME: This is incorrect see PR642.
|
|
case ISD::SETUGE:
|
|
case ISD::SETGE: return PPC::PRED_GE;
|
|
|
|
case ISD::SETO: return PPC::PRED_NU;
|
|
case ISD::SETUO: return PPC::PRED_UN;
|
|
}
|
|
}
|
|
|
|
/// getCRIdxForSetCC - Return the index of the condition register field
|
|
/// associated with the SetCC condition, and whether or not the field is
|
|
/// treated as inverted. That is, lt = 0; ge = 0 inverted.
|
|
///
|
|
/// If this returns with Other != -1, then the returned comparison is an or of
|
|
/// two simpler comparisons. In this case, Invert is guaranteed to be false.
|
|
static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
|
|
Invert = false;
|
|
Other = -1;
|
|
switch (CC) {
|
|
default: assert(0 && "Unknown condition!"); abort();
|
|
case ISD::SETOLT:
|
|
case ISD::SETLT: return 0; // Bit #0 = SETOLT
|
|
case ISD::SETOGT:
|
|
case ISD::SETGT: return 1; // Bit #1 = SETOGT
|
|
case ISD::SETOEQ:
|
|
case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
|
|
case ISD::SETUO: return 3; // Bit #3 = SETUO
|
|
case ISD::SETUGE:
|
|
case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
|
|
case ISD::SETULE:
|
|
case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
|
|
case ISD::SETUNE:
|
|
case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
|
|
case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
|
|
case ISD::SETULT: Other = 0; return 3; // SETOLT | SETUO
|
|
case ISD::SETUGT: Other = 1; return 3; // SETOGT | SETUO
|
|
case ISD::SETUEQ: Other = 2; return 3; // SETOEQ | SETUO
|
|
case ISD::SETOGE: Other = 1; return 2; // SETOGT | SETOEQ
|
|
case ISD::SETOLE: Other = 0; return 2; // SETOLT | SETOEQ
|
|
case ISD::SETONE: Other = 0; return 1; // SETOLT | SETOGT
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
unsigned Imm;
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
|
|
if (isInt32Immediate(N->getOperand(1), Imm)) {
|
|
// We can codegen setcc op, imm very efficiently compared to a brcond.
|
|
// Check for those cases here.
|
|
// setcc op, 0
|
|
if (Imm == 0) {
|
|
SDOperand Op = N->getOperand(0);
|
|
AddToISelQueue(Op);
|
|
switch (CC) {
|
|
default: break;
|
|
case ISD::SETEQ: {
|
|
Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
|
|
SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
case ISD::SETNE: {
|
|
SDOperand AD =
|
|
SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
Op, getI32Imm(~0U)), 0);
|
|
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
|
|
AD.getValue(1));
|
|
}
|
|
case ISD::SETLT: {
|
|
SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
case ISD::SETGT: {
|
|
SDOperand T =
|
|
SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
|
|
T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
|
|
SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
}
|
|
} else if (Imm == ~0U) { // setcc op, -1
|
|
SDOperand Op = N->getOperand(0);
|
|
AddToISelQueue(Op);
|
|
switch (CC) {
|
|
default: break;
|
|
case ISD::SETEQ:
|
|
Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
Op, getI32Imm(1)), 0);
|
|
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
|
|
SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
|
|
getI32Imm(0)), 0),
|
|
Op.getValue(1));
|
|
case ISD::SETNE: {
|
|
Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
|
|
SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
Op, getI32Imm(~0U));
|
|
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
|
|
Op, SDOperand(AD, 1));
|
|
}
|
|
case ISD::SETLT: {
|
|
SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
|
|
getI32Imm(1)), 0);
|
|
SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
|
|
Op), 0);
|
|
SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
case ISD::SETGT: {
|
|
SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
|
|
Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
|
|
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
|
|
getI32Imm(1));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
bool Inv;
|
|
int OtherCondIdx;
|
|
unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
|
|
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
|
|
SDOperand IntCR;
|
|
|
|
// Force the ccreg into CR7.
|
|
SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
|
|
|
|
SDOperand InFlag(0, 0); // Null incoming flag value.
|
|
CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
|
|
InFlag).getValue(1);
|
|
|
|
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
|
|
IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
|
|
CCReg), 0);
|
|
else
|
|
IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
|
|
|
|
SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
|
|
getI32Imm(31), getI32Imm(31) };
|
|
if (OtherCondIdx == -1 && !Inv)
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
|
|
// Get the specified bit.
|
|
SDOperand Tmp =
|
|
SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
|
|
if (Inv) {
|
|
assert(OtherCondIdx == -1 && "Can't have split plus negation");
|
|
return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
|
|
}
|
|
|
|
// Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
|
|
// We already got the bit for the first part of the comparison (e.g. SETULE).
|
|
|
|
// Get the other bit of the comparison.
|
|
Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
|
|
SDOperand OtherCond =
|
|
SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
|
|
|
|
return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
|
|
}
|
|
|
|
|
|
// Select - Convert the specified operand from a target-independent to a
|
|
// target-specific node if it hasn't already been changed.
|
|
SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
|
|
N->getOpcode() < PPCISD::FIRST_NUMBER)
|
|
return NULL; // Already selected.
|
|
|
|
switch (N->getOpcode()) {
|
|
default: break;
|
|
|
|
case ISD::Constant: {
|
|
if (N->getValueType(0) == MVT::i64) {
|
|
// Get 64 bit value.
|
|
int64_t Imm = cast<ConstantSDNode>(N)->getValue();
|
|
// Assume no remaining bits.
|
|
unsigned Remainder = 0;
|
|
// Assume no shift required.
|
|
unsigned Shift = 0;
|
|
|
|
// If it can't be represented as a 32 bit value.
|
|
if (!isInt32(Imm)) {
|
|
Shift = CountTrailingZeros_64(Imm);
|
|
int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
|
|
|
|
// If the shifted value fits 32 bits.
|
|
if (isInt32(ImmSh)) {
|
|
// Go with the shifted value.
|
|
Imm = ImmSh;
|
|
} else {
|
|
// Still stuck with a 64 bit value.
|
|
Remainder = Imm;
|
|
Shift = 32;
|
|
Imm >>= 32;
|
|
}
|
|
}
|
|
|
|
// Intermediate operand.
|
|
SDNode *Result;
|
|
|
|
// Handle first 32 bits.
|
|
unsigned Lo = Imm & 0xFFFF;
|
|
unsigned Hi = (Imm >> 16) & 0xFFFF;
|
|
|
|
// Simple value.
|
|
if (isInt16(Imm)) {
|
|
// Just the Lo bits.
|
|
Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
|
|
} else if (Lo) {
|
|
// Handle the Hi bits.
|
|
unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
|
|
Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
|
|
// And Lo bits.
|
|
Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
|
|
SDOperand(Result, 0), getI32Imm(Lo));
|
|
} else {
|
|
// Just the Hi bits.
|
|
Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
|
|
}
|
|
|
|
// If no shift, we're done.
|
|
if (!Shift) return Result;
|
|
|
|
// Shift for next step if the upper 32-bits were not zero.
|
|
if (Imm) {
|
|
Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
|
|
SDOperand(Result, 0),
|
|
getI32Imm(Shift), getI32Imm(63 - Shift));
|
|
}
|
|
|
|
// Add in the last bits as required.
|
|
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
|
|
Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
|
|
SDOperand(Result, 0), getI32Imm(Hi));
|
|
}
|
|
if ((Lo = Remainder & 0xFFFF)) {
|
|
Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
|
|
SDOperand(Result, 0), getI32Imm(Lo));
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case ISD::SETCC:
|
|
return SelectSETCC(Op);
|
|
case PPCISD::GlobalBaseReg:
|
|
return getGlobalBaseReg();
|
|
|
|
case ISD::FrameIndex: {
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
|
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
|
|
unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
|
|
if (N->hasOneUse())
|
|
return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
|
|
getSmallIPtrImm(0));
|
|
return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
|
|
getSmallIPtrImm(0));
|
|
}
|
|
|
|
case PPCISD::MFCR: {
|
|
SDOperand InFlag = N->getOperand(1);
|
|
AddToISelQueue(InFlag);
|
|
// Use MFOCRF if supported.
|
|
if (PPCSubTarget.isGigaProcessor())
|
|
return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
|
|
N->getOperand(0), InFlag);
|
|
else
|
|
return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
|
|
}
|
|
|
|
case ISD::SDIV: {
|
|
// FIXME: since this depends on the setting of the carry flag from the srawi
|
|
// we should really be making notes about that for the scheduler.
|
|
// FIXME: It sure would be nice if we could cheaply recognize the
|
|
// srl/add/sra pattern the dag combiner will generate for this as
|
|
// sra/addze rather than having to handle sdiv ourselves. oh well.
|
|
unsigned Imm;
|
|
if (isInt32Immediate(N->getOperand(1), Imm)) {
|
|
SDOperand N0 = N->getOperand(0);
|
|
AddToISelQueue(N0);
|
|
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
|
|
SDNode *Op =
|
|
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
|
|
N0, getI32Imm(Log2_32(Imm)));
|
|
return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
|
|
SDOperand(Op, 0), SDOperand(Op, 1));
|
|
} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
|
|
SDNode *Op =
|
|
CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
|
|
N0, getI32Imm(Log2_32(-Imm)));
|
|
SDOperand PT =
|
|
SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
|
|
SDOperand(Op, 0), SDOperand(Op, 1)),
|
|
0);
|
|
return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
|
|
}
|
|
}
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
|
|
case ISD::LOAD: {
|
|
// Handle preincrement loads.
|
|
LoadSDNode *LD = cast<LoadSDNode>(Op);
|
|
MVT::ValueType LoadedVT = LD->getMemoryVT();
|
|
|
|
// Normal loads are handled by code generated from the .td file.
|
|
if (LD->getAddressingMode() != ISD::PRE_INC)
|
|
break;
|
|
|
|
SDOperand Offset = LD->getOffset();
|
|
if (isa<ConstantSDNode>(Offset) ||
|
|
Offset.getOpcode() == ISD::TargetGlobalAddress) {
|
|
|
|
unsigned Opcode;
|
|
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
|
|
if (LD->getValueType(0) != MVT::i64) {
|
|
// Handle PPC32 integer and normal FP loads.
|
|
assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
|
|
switch (LoadedVT) {
|
|
default: assert(0 && "Invalid PPC load type!");
|
|
case MVT::f64: Opcode = PPC::LFDU; break;
|
|
case MVT::f32: Opcode = PPC::LFSU; break;
|
|
case MVT::i32: Opcode = PPC::LWZU; break;
|
|
case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
|
|
case MVT::i1:
|
|
case MVT::i8: Opcode = PPC::LBZU; break;
|
|
}
|
|
} else {
|
|
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
|
|
assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
|
|
switch (LoadedVT) {
|
|
default: assert(0 && "Invalid PPC load type!");
|
|
case MVT::i64: Opcode = PPC::LDU; break;
|
|
case MVT::i32: Opcode = PPC::LWZU8; break;
|
|
case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
|
|
case MVT::i1:
|
|
case MVT::i8: Opcode = PPC::LBZU8; break;
|
|
}
|
|
}
|
|
|
|
SDOperand Chain = LD->getChain();
|
|
SDOperand Base = LD->getBasePtr();
|
|
AddToISelQueue(Chain);
|
|
AddToISelQueue(Base);
|
|
AddToISelQueue(Offset);
|
|
SDOperand Ops[] = { Offset, Base, Chain };
|
|
// FIXME: PPC64
|
|
return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
|
|
MVT::Other, Ops, 3);
|
|
} else {
|
|
assert(0 && "R+R preindex loads not supported yet!");
|
|
}
|
|
}
|
|
|
|
case ISD::AND: {
|
|
unsigned Imm, Imm2, SH, MB, ME;
|
|
|
|
// If this is an and of a value rotated between 0 and 31 bits and then and'd
|
|
// with a mask, emit rlwinm
|
|
if (isInt32Immediate(N->getOperand(1), Imm) &&
|
|
isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
|
|
SDOperand Val = N->getOperand(0).getOperand(0);
|
|
AddToISelQueue(Val);
|
|
SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
// If this is just a masked value where the input is not handled above, and
|
|
// is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
|
|
if (isInt32Immediate(N->getOperand(1), Imm) &&
|
|
isRunOfOnes(Imm, MB, ME) &&
|
|
N->getOperand(0).getOpcode() != ISD::ROTL) {
|
|
SDOperand Val = N->getOperand(0);
|
|
AddToISelQueue(Val);
|
|
SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
// AND X, 0 -> 0, not "rlwinm 32".
|
|
if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
|
|
AddToISelQueue(N->getOperand(1));
|
|
ReplaceUses(SDOperand(N, 0), N->getOperand(1));
|
|
return NULL;
|
|
}
|
|
// ISD::OR doesn't get all the bitfield insertion fun.
|
|
// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
|
|
if (isInt32Immediate(N->getOperand(1), Imm) &&
|
|
N->getOperand(0).getOpcode() == ISD::OR &&
|
|
isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
|
|
unsigned MB, ME;
|
|
Imm = ~(Imm^Imm2);
|
|
if (isRunOfOnes(Imm, MB, ME)) {
|
|
AddToISelQueue(N->getOperand(0).getOperand(0));
|
|
AddToISelQueue(N->getOperand(0).getOperand(1));
|
|
SDOperand Ops[] = { N->getOperand(0).getOperand(0),
|
|
N->getOperand(0).getOperand(1),
|
|
getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
|
|
return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
|
|
}
|
|
}
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
case ISD::OR:
|
|
if (N->getValueType(0) == MVT::i32)
|
|
if (SDNode *I = SelectBitfieldInsert(N))
|
|
return I;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
case ISD::SHL: {
|
|
unsigned Imm, SH, MB, ME;
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
|
|
AddToISelQueue(N->getOperand(0).getOperand(0));
|
|
SDOperand Ops[] = { N->getOperand(0).getOperand(0),
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
case ISD::SRL: {
|
|
unsigned Imm, SH, MB, ME;
|
|
if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
|
|
isRotateAndMask(N, Imm, true, SH, MB, ME)) {
|
|
AddToISelQueue(N->getOperand(0).getOperand(0));
|
|
SDOperand Ops[] = { N->getOperand(0).getOperand(0),
|
|
getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
|
|
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
|
|
}
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
case ISD::SELECT_CC: {
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
|
|
|
|
// Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
|
|
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
|
|
if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
|
|
if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
|
|
if (N1C->isNullValue() && N3C->isNullValue() &&
|
|
N2C->getValue() == 1ULL && CC == ISD::SETNE &&
|
|
// FIXME: Implement this optzn for PPC64.
|
|
N->getValueType(0) == MVT::i32) {
|
|
AddToISelQueue(N->getOperand(0));
|
|
SDNode *Tmp =
|
|
CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
|
|
N->getOperand(0), getI32Imm(~0U));
|
|
return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
|
|
SDOperand(Tmp, 0), N->getOperand(0),
|
|
SDOperand(Tmp, 1));
|
|
}
|
|
|
|
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
|
|
unsigned BROpc = getPredicateForSetCC(CC);
|
|
|
|
unsigned SelectCCOp;
|
|
if (N->getValueType(0) == MVT::i32)
|
|
SelectCCOp = PPC::SELECT_CC_I4;
|
|
else if (N->getValueType(0) == MVT::i64)
|
|
SelectCCOp = PPC::SELECT_CC_I8;
|
|
else if (N->getValueType(0) == MVT::f32)
|
|
SelectCCOp = PPC::SELECT_CC_F4;
|
|
else if (N->getValueType(0) == MVT::f64)
|
|
SelectCCOp = PPC::SELECT_CC_F8;
|
|
else
|
|
SelectCCOp = PPC::SELECT_CC_VRRC;
|
|
|
|
AddToISelQueue(N->getOperand(2));
|
|
AddToISelQueue(N->getOperand(3));
|
|
SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
|
|
getI32Imm(BROpc) };
|
|
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
|
|
}
|
|
case PPCISD::COND_BRANCH: {
|
|
AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
|
|
// Op #1 is the PPC::PRED_* number.
|
|
// Op #2 is the CR#
|
|
// Op #3 is the Dest MBB
|
|
AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
|
|
// Prevent PPC::PRED_* from being selected into LI.
|
|
SDOperand Pred =
|
|
getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue());
|
|
SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
|
|
N->getOperand(0), N->getOperand(4) };
|
|
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
|
|
}
|
|
case ISD::BR_CC: {
|
|
AddToISelQueue(N->getOperand(0));
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
|
|
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
|
|
SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
|
|
N->getOperand(4), N->getOperand(0) };
|
|
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
|
|
}
|
|
case ISD::BRIND: {
|
|
// FIXME: Should custom lower this.
|
|
SDOperand Chain = N->getOperand(0);
|
|
SDOperand Target = N->getOperand(1);
|
|
AddToISelQueue(Chain);
|
|
AddToISelQueue(Target);
|
|
unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
|
|
Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
|
|
Chain), 0);
|
|
return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
|
|
}
|
|
}
|
|
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
|
|
|
|
/// createPPCISelDag - This pass converts a legalized DAG into a
|
|
/// PowerPC-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
|
|
return new PPCDAGToDAGISel(TM);
|
|
}
|
|
|