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https://github.com/c64scene-ar/llvm-6502.git
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ed788b6283
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181801 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.2 KiB
LLVM
62 lines
2.2 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
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@g = global i32 0, align 4
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define i32 @LoadGV() {
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entry:
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; THUMB: LoadGV
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; THUMB: movw [[reg0:r[0-9]+]],
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; THUMB: movt [[reg0]],
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; THUMB: add [[reg0]], pc
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; THUMB-ELF: LoadGV
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; THUMB-ELF: ldr.n r[[reg0:[0-9]+]],
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; THUMB-ELF: ldr.n r[[reg1:[0-9]+]],
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; THUMB-ELF: ldr r[[reg0]], [r[[reg1]], r[[reg0]]]
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; ARM: LoadGV
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; ARM: ldr [[reg1:r[0-9]+]],
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; ARM: add [[reg1]], pc, [[reg1]]
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; ARMv7: LoadGV
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; ARMv7: movw [[reg2:r[0-9]+]],
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; ARMv7: movt [[reg2]],
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; ARMv7: add [[reg2]], pc, [[reg2]]
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; ARMv7-ELF: LoadGV
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; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
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; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
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; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
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%tmp = load i32* @g
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ret i32 %tmp
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}
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@i = external global i32
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define i32 @LoadIndirectSymbol() {
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entry:
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; THUMB: LoadIndirectSymbol
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; THUMB: movw r[[reg3:[0-9]+]],
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; THUMB: movt r[[reg3]],
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; THUMB: add r[[reg3]], pc
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; THUMB: ldr r[[reg3]], [r[[reg3]]]
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; THUMB-ELF: LoadIndirectSymbol
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; THUMB-ELF: ldr.n r[[reg3:[0-9]+]],
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; THUMB-ELF: ldr.n r[[reg4:[0-9]+]],
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; THUMB-ELF: ldr r[[reg3]], [r[[reg4]], r[[reg3]]]
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; ARM: LoadIndirectSymbol
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; ARM: ldr [[reg4:r[0-9]+]],
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; ARM: ldr [[reg4]], [pc, [[reg4]]]
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; ARMv7: LoadIndirectSymbol
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; ARMv7: movw r[[reg5:[0-9]+]],
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; ARMv7: movt r[[reg5]],
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; ARMv7: add r[[reg5]], pc, r[[reg5]]
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; ARMv7: ldr r[[reg5]], [r[[reg5]]]
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; ARMv7-ELF: LoadIndirectSymbol
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; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
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; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
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; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
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%tmp = load i32* @i
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ret i32 %tmp
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}
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