llvm-6502/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

30 lines
889 B
LLVM

; RUN: llc -march=arm64 -mcpu=cyclone < %s | FileCheck %s
; CHECK: foo
; CHECK: ldr w[[REG:[0-9]+]], [x19, #264]
; CHECK: str w[[REG]], [x19, #132]
; CHECK: ldr w{{[0-9]+}}, [x19, #264]
define i32 @foo(i32 %a) nounwind {
%retval = alloca i32, align 4
%a.addr = alloca i32, align 4
%arr = alloca [32 x i32], align 4
%i = alloca i32, align 4
%arr2 = alloca [32 x i32], align 4
%j = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%tmp = load i32, i32* %a.addr, align 4
%tmp1 = zext i32 %tmp to i64
%v = mul i64 4, %tmp1
%vla = alloca i8, i64 %v, align 4
%tmp2 = bitcast i8* %vla to i32*
%tmp3 = load i32, i32* %a.addr, align 4
store i32 %tmp3, i32* %i, align 4
%tmp4 = load i32, i32* %a.addr, align 4
store i32 %tmp4, i32* %j, align 4
%tmp5 = load i32, i32* %j, align 4
store i32 %tmp5, i32* %retval
%x = load i32, i32* %retval
ret i32 %x
}