mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.1 KiB
LLVM
113 lines
4.1 KiB
LLVM
; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
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%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
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@src = external global %struct.x
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@dst = external global %struct.x
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@.str1 = private unnamed_addr constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 1
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@.str2 = private unnamed_addr constant [36 x i8] c"DHRYSTONE PROGRAM, SOME STRING BLAH\00", align 1
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@.str3 = private unnamed_addr constant [24 x i8] c"DHRYSTONE PROGRAM, SOME\00", align 1
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@.str4 = private unnamed_addr constant [18 x i8] c"DHRYSTONE PROGR \00", align 1
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@.str5 = private unnamed_addr constant [7 x i8] c"DHRYST\00", align 1
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@.str6 = private unnamed_addr constant [14 x i8] c"/tmp/rmXXXXXX\00", align 1
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@spool.splbuf = internal global [512 x i8] zeroinitializer, align 16
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define i32 @t0() {
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entry:
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; CHECK-LABEL: t0:
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; CHECK: ldrb [[REG0:w[0-9]+]], [x[[BASEREG:[0-9]+]], #10]
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; CHECK: strb [[REG0]], [x[[BASEREG2:[0-9]+]], #10]
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; CHECK: ldrh [[REG1:w[0-9]+]], [x[[BASEREG]], #8]
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; CHECK: strh [[REG1]], [x[[BASEREG2]], #8]
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; CHECK: ldr [[REG2:x[0-9]+]],
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; CHECK: str [[REG2]],
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
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ret i32 0
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}
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define void @t1(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: ldur [[DEST:q[0-9]+]], [x[[BASEREG:[0-9]+]], #15]
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; CHECK: stur [[DEST]], [x0, #15]
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; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]
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; CHECK: str [[DEST]], [x0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
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ret void
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}
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define void @t2(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: movz [[REG3:w[0-9]+]]
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; CHECK: movk [[REG3]],
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; CHECK: str [[REG3]], [x0, #32]
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; CHECK: ldp [[DEST1:q[0-9]+]], [[DEST2:q[0-9]+]], [x{{[0-9]+}}]
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; CHECK: stp [[DEST1]], [[DEST2]], [x0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
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ret void
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}
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define void @t3(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: ldr [[REG4:x[0-9]+]], [x[[BASEREG:[0-9]+]], #16]
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; CHECK: str [[REG4]], [x0, #16]
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; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]
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; CHECK: str [[DEST]], [x0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
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ret void
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}
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define void @t4(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x20
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; CHECK: strh [[REG5]], [x0, #16]
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; CHECK: ldr [[REG6:q[0-9]+]], [x{{[0-9]+}}]
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; CHECK: str [[REG6]], [x0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
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ret void
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}
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define void @t5(i8* nocapture %C) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: strb wzr, [x0, #6]
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; CHECK: movz [[REG7:w[0-9]+]], #0x5453
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; CHECK: strh [[REG7]], [x0, #4]
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; CHECK: movz [[REG8:w[0-9]+]],
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; CHECK: movk [[REG8]],
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; CHECK: str [[REG8]], [x0]
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
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ret void
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}
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define void @t6() nounwind {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: ldur [[REG9:x[0-9]+]], [x{{[0-9]+}}, #6]
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; CHECK: stur [[REG9]], [x{{[0-9]+}}, #6]
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; CHECK: ldr
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; CHECK: str
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
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ret void
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}
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%struct.Foo = type { i32, i32, i32, i32 }
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define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
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entry:
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; CHECK: t7
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; CHECK: ldr [[REG10:q[0-9]+]], [x1]
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; CHECK: str [[REG10]], [x0]
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%0 = bitcast %struct.Foo* %a to i8*
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%1 = bitcast %struct.Foo* %b to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 16, i32 4, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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