mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
e3a804ba21
Since z has no setcc instruction as such, the choice of setBooleanContents is a bit arbitrary. Currently it's set to ZeroOrOneBooleanContent, so we produced a branch-free form when selecting between 0 and 1, but not when selecting between 0 and -1. This patch handles the latter case too. At some point I'd like to measure whether it's better to use conditional moves for constant selects on z196, but that's future work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196578 91177308-0d34-0410-b5e6-96231b3b80d8
188 lines
4.7 KiB
LLVM
188 lines
4.7 KiB
LLVM
; Test an i64 0/-1 SELECTCCC for every floating-point condition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test CC in { 0 }
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define i64 @f1(float %a, float %b) {
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; CHECK-LABEL: f1:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], -268435456
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp oeq float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 1 }
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define i64 @f2(float %a, float %b) {
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; CHECK-LABEL: f2:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: xilf [[REG]], 268435456
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; CHECK-NEXT: afi [[REG]], -268435456
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp olt float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 0, 1 }
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define i64 @f3(float %a, float %b) {
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; CHECK-LABEL: f3:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], -536870912
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ole float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 2 }
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define i64 @f4(float %a, float %b) {
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; CHECK-LABEL: f4:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: xilf [[REG]], 268435456
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; CHECK-NEXT: afi [[REG]], 1342177280
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ogt float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 0, 2 }
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define i64 @f5(float %a, float %b) {
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; CHECK-LABEL: f5:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: xilf [[REG]], 4294967295
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; CHECK-NEXT: sllg [[REG]], [[REG]], 35
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp oge float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 1, 2 }
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define i64 @f6(float %a, float %b) {
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; CHECK-LABEL: f6:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], 268435456
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; CHECK-NEXT: sllg [[REG]], [[REG]], 34
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp one float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 0, 1, 2 }
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define i64 @f7(float %a, float %b) {
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; CHECK-LABEL: f7:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], -805306368
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ord float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 3 }
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define i64 @f8(float %a, float %b) {
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; CHECK-LABEL: f8:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], 1342177280
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp uno float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 0, 3 }
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define i64 @f9(float %a, float %b) {
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; CHECK-LABEL: f9:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], -268435456
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; CHECK-NEXT: sllg [[REG]], [[REG]], 34
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ueq float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 1, 3 }
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define i64 @f10(float %a, float %b) {
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; CHECK-LABEL: f10:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: sllg [[REG]], [[REG]], 35
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ult float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 0, 1, 3 }
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define i64 @f11(float %a, float %b) {
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; CHECK-LABEL: f11:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: xilf [[REG]], 268435456
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; CHECK-NEXT: afi [[REG]], -805306368
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ule float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 2, 3 }
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define i64 @f12(float %a, float %b) {
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; CHECK-LABEL: f12:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: sllg [[REG]], [[REG]], 34
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp ugt float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 0, 2, 3 }
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define i64 @f13(float %a, float %b) {
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; CHECK-LABEL: f13:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: xilf [[REG]], 268435456
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; CHECK-NEXT: afi [[REG]], 1879048192
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp uge float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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; Test CC in { 1, 2, 3 }
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define i64 @f14(float %a, float %b) {
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; CHECK-LABEL: f14:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK-NEXT: afi [[REG]], 1879048192
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; CHECK-NEXT: sllg [[REG]], [[REG]], 32
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; CHECK-NEXT: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%cond = fcmp une float %a, %b
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%res = select i1 %cond, i64 -1, i64 0
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ret i64 %res
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}
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