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https://github.com/c64scene-ar/llvm-6502.git
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12f33da20b
On AArch64 the pseudo instruction ldr <reg>, =... supports both 32-bit and 64-bit constants. Add support for 64 bit constants for the pools to support the pseudo instruction fully. Changes the AArch64 ldr-pseudo tests to use 32-bit registers and adds tests with 64-bit registers. Patch by Janne Grunau! Differential Revision: http://reviews.llvm.org/D4279 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213387 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
441 B
ArmAsm
15 lines
441 B
ArmAsm
//RUN: not llvm-mc -triple=aarch64-linux-gnu - < %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
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// simple test
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.section a, "ax", @progbits
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f1:
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ldr w0, =0x100000001
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// CHECK-ERROR: error: Immediate too large for register
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// CHECK-ERROR: ldr w0, =0x100000001
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// CHECK-ERROR: ^
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f2:
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ldr w0, =-0x80000001
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// CHECK-ERROR: error: Immediate too large for register
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// CHECK-ERROR: ldr w0, =-0x80000001
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// CHECK-ERROR: ^
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