mirror of
https://github.com/c64scene-ar/llvm-6502.git
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21e3dfbc86
- Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.8 KiB
LLVM
41 lines
1.8 KiB
LLVM
; RUN: llvm-as < %s | llc -mtriple=i386-unknown-linux-gnu
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; PR3391
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@pci_indirect = external global { } ; <{ }*> [#uses=1]
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@pcibios_last_bus = external global i32 ; <i32*> [#uses=2]
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define void @pci_pcbios_init() nounwind section ".init.text" {
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entry:
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br label %bb1.i
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bb1.i: ; preds = %bb6.i.i, %bb1.i, %entry
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%0 = load i32* null, align 8 ; <i32> [#uses=1]
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%1 = icmp ugt i32 %0, 1048575 ; <i1> [#uses=1]
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br i1 %1, label %bb2.i, label %bb1.i
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bb2.i: ; preds = %bb1.i
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%asmtmp.i.i = tail call { i32, i32, i32, i32 } asm "lcall *(%edi); cld\0A\09jc 1f\0A\09xor %ah, %ah\0A1:", "={dx},={ax},={bx},={cx},1,{di},~{dirflag},~{fpsr},~{flags},~{memory}"(i32 45313, { }* @pci_indirect) nounwind ; <{ i32, i32, i32, i32 }> [#uses=2]
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%asmresult2.i.i = extractvalue { i32, i32, i32, i32 } %asmtmp.i.i, 1
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; <i32> [#uses=1]
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%2 = lshr i32 %asmresult2.i.i, 8 ; <i32> [#uses=1]
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%3 = trunc i32 %2 to i8 ; <i8> [#uses=1]
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%4 = load i32* @pcibios_last_bus, align 4 ; <i32> [#uses=1]
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%5 = icmp slt i32 %4, 0 ; <i1> [#uses=1]
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br i1 %5, label %bb5.i.i, label %bb6.i.i
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bb5.i.i: ; preds = %bb2.i
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%asmresult4.i.i = extractvalue { i32, i32, i32, i32 } %asmtmp.i.i, 3
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; <i32> [#uses=1]
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%6 = and i32 %asmresult4.i.i, 255 ; <i32> [#uses=1]
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store i32 %6, i32* @pcibios_last_bus, align 4
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br label %bb6.i.i
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bb6.i.i: ; preds = %bb5.i.i, %bb2.i
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%7 = icmp eq i8 %3, 0 ; <i1> [#uses=1]
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%or.cond.i.i = and i1 %7, false ; <i1> [#uses=1]
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br i1 %or.cond.i.i, label %bb1.i, label %bb8.i.i
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bb8.i.i: ; preds = %bb6.i.i
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unreachable
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}
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