mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
4d7af65903
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
417 lines
15 KiB
C++
417 lines
15 KiB
C++
//===-- PeepholeOptimizer.cpp - X86 Peephole Optimizer --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a peephole optimizer for the X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "Support/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<> NumPHOpts("x86-peephole",
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"Number of peephole optimization performed");
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struct PH : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
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};
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}
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FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
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bool PH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I)) {
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Changed = true;
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++NumPHOpts;
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} else
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++I;
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return Changed;
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}
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bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = *I;
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MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
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unsigned Size = 0;
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switch (MI->getOpcode()) {
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case X86::MOVrr8:
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case X86::MOVrr16:
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case X86::MOVrr32: // Destroy X = X copies...
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if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
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I = MBB.erase(I);
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delete MI;
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return true;
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}
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return false;
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// A large number of X86 instructions have forms which take an 8-bit
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// immediate despite the fact that the operands are 16 or 32 bits. Because
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// this can save three bytes of code size (and icache space), we want to
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// shrink them if possible.
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case X86::ADDri16: case X86::ADDri32:
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case X86::SUBri16: case X86::SUBri32:
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case X86::IMULri16: case X86::IMULri32:
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case X86::ANDri16: case X86::ANDri32:
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case X86::ORri16: case X86::ORri32:
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case X86::XORri16: case X86::XORri32:
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assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
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if (MI->getOperand(2).isImmediate()) {
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int Val = MI->getOperand(2).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::ADDri16: Opcode = X86::ADDri16b; break;
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case X86::ADDri32: Opcode = X86::ADDri32b; break;
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case X86::SUBri16: Opcode = X86::SUBri16b; break;
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case X86::SUBri32: Opcode = X86::SUBri32b; break;
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case X86::IMULri16: Opcode = X86::IMULri16b; break;
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case X86::IMULri32: Opcode = X86::IMULri32b; break;
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case X86::ANDri16: Opcode = X86::ANDri16b; break;
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case X86::ANDri32: Opcode = X86::ANDri32b; break;
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case X86::ORri16: Opcode = X86::ORri16b; break;
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case X86::ORri32: Opcode = X86::ORri32b; break;
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case X86::XORri16: Opcode = X86::XORri16b; break;
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case X86::XORri32: Opcode = X86::XORri32b; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned R1 = MI->getOperand(1).getReg();
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*I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
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delete MI;
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return true;
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}
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}
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return false;
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#if 0
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case X86::MOVir32: Size++;
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case X86::MOVir16: Size++;
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case X86::MOVir8:
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// FIXME: We can only do this transformation if we know that flags are not
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// used here, because XOR clobbers the flags!
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if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
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int Val = MI->getOperand(1).getImmedValue();
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if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
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static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
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unsigned Reg = MI->getOperand(0).getReg();
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*I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
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delete MI;
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return true;
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} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
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// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
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}
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}
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return false;
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#endif
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case X86::BSWAPr32: // Change bswap EAX, bswap EAX into nothing
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if (Next->getOpcode() == X86::BSWAPr32 &&
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MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
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I = MBB.erase(MBB.erase(I));
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delete MI;
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delete Next;
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return true;
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}
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return false;
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default:
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return false;
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}
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}
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namespace {
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class UseDefChains : public MachineFunctionPass {
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std::vector<MachineInstr*> DefiningInst;
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public:
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// getDefinition - Return the machine instruction that defines the specified
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// SSA virtual register.
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MachineInstr *getDefinition(unsigned Reg) {
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assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
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"use-def chains only exist for SSA registers!");
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assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
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"Unknown register number!");
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assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
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"Unknown register number!");
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return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
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}
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// setDefinition - Update the use-def chains to indicate that MI defines
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// register Reg.
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void setDefinition(unsigned Reg, MachineInstr *MI) {
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if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
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DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
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}
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// removeDefinition - Update the use-def chains to forget about Reg
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// entirely.
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void removeDefinition(unsigned Reg) {
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assert(getDefinition(Reg)); // Check validity
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
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}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
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MachineInstr *MI = *I;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isVirtualRegister() && MO.isDef() && !MO.isUse())
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setDefinition(MO.getReg(), MI);
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}
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}
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return false;
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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std::vector<MachineInstr*>().swap(DefiningInst);
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}
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};
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RegisterAnalysis<UseDefChains> X("use-def-chains",
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"use-def chain construction for machine code");
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}
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namespace {
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Statistic<> NumSSAPHOpts("x86-ssa-peephole",
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"Number of SSA peephole optimization performed");
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/// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
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/// pass is really a bad idea: a better instruction selector should completely
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/// supersume it. However, that will take some time to develop, and the
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/// simple things this can do are important now.
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class SSAPH : public MachineFunctionPass {
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UseDefChains *UDC;
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public:
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const {
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return "X86 SSA-based Peephole Optimizer";
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}
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/// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
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/// opcode of the instruction, then return true.
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bool Propagate(MachineInstr *MI, unsigned DestOpNo,
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MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
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MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
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if (NewOpcode) MI->setOpcode(NewOpcode);
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return true;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
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/// getDefininingInst - If the specified operand is a read of an SSA
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/// register, return the machine instruction defining it, otherwise, return
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/// null.
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MachineInstr *getDefiningInst(MachineOperand &MO) {
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if (MO.isDef() || !MO.isVirtualRegister()) return 0;
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return UDC->getDefinition(MO.getReg());
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<UseDefChains>();
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AU.addPreserved<UseDefChains>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
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bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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bool LocalChanged;
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UDC = &getAnalysis<UseDefChains>();
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do {
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LocalChanged = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I)) {
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LocalChanged = true;
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++NumSSAPHOpts;
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} else
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++I;
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Changed |= LocalChanged;
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} while (LocalChanged);
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return Changed;
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}
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static bool isValidScaleAmount(unsigned Scale) {
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return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
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MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
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MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
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MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
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MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
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unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
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unsigned Scale = ScaleOp.getImmedValue();
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unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
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bool Changed = false;
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// If the base register is unset, and the index register is set with a scale
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// of 1, move it to be the base register.
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if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
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Scale == 1 && IndexReg != 0) {
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BaseRegOp.setReg(IndexReg);
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IndexRegOp.setReg(0);
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return true;
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}
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// Attempt to fold instructions used by the base register into the instruction
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if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
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switch (DefInst->getOpcode()) {
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case X86::MOVir32:
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// If there is no displacement set for this instruction set one now.
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// FIXME: If we can fold two immediates together, we should do so!
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if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
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if (DefInst->getOperand(1).isImmediate()) {
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BaseRegOp.setReg(0);
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return Propagate(MI, OpNo+3, DefInst, 1);
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}
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}
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break;
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case X86::ADDrr32:
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// If the source is a register-register add, and we do not yet have an
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// index register, fold the add into the memory address.
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if (IndexReg == 0) {
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BaseRegOp = DefInst->getOperand(1);
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IndexRegOp = DefInst->getOperand(2);
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ScaleOp.setImmedValue(1);
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return true;
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}
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break;
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case X86::SHLir32:
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// If this shift could be folded into the index portion of the address if
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// it were the index register, move it to the index register operand now,
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// so it will be folded in below.
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if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
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DefInst->getOperand(2).getImmedValue() < 4) {
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std::swap(BaseRegOp, IndexRegOp);
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ScaleOp.setImmedValue(1); Scale = 1;
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std::swap(IndexReg, BaseReg);
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Changed = true;
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break;
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}
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}
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}
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// Attempt to fold instructions used by the index into the instruction
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if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
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switch (DefInst->getOpcode()) {
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case X86::SHLir32: {
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// Figure out what the resulting scale would be if we folded this shift.
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unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
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if (isValidScaleAmount(ResScale)) {
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IndexRegOp = DefInst->getOperand(1);
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ScaleOp.setImmedValue(ResScale);
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return true;
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}
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break;
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}
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}
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}
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return Changed;
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}
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bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = *I;
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MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
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bool Changed = false;
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// Scan the operands of this instruction. If any operands are
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// register-register copies, replace the operand with the source.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
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// Is this an SSA register use?
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if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i)))
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// If the operand is a vreg-vreg copy, it is always safe to replace the
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// source value with the input operand.
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if (DefInst->getOpcode() == X86::MOVrr8 ||
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DefInst->getOpcode() == X86::MOVrr16 ||
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DefInst->getOpcode() == X86::MOVrr32) {
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// Don't propagate physical registers into PHI nodes...
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if (MI->getOpcode() != X86::PHI ||
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DefInst->getOperand(1).isVirtualRegister())
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Changed = Propagate(MI, i, DefInst, 1);
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}
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// Perform instruction specific optimizations.
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switch (MI->getOpcode()) {
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// Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
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case X86::MOVrm32: case X86::MOVrm16: case X86::MOVrm8:
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case X86::MOVim32: case X86::MOVim16: case X86::MOVim8:
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// Check to see if we can fold the source instruction into this one...
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if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
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switch (SrcInst->getOpcode()) {
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// Fold the immediate value into the store, if possible.
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case X86::MOVir8: return Propagate(MI, 4, SrcInst, 1, X86::MOVim8);
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case X86::MOVir16: return Propagate(MI, 4, SrcInst, 1, X86::MOVim16);
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case X86::MOVir32: return Propagate(MI, 4, SrcInst, 1, X86::MOVim32);
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default: break;
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}
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}
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// If we can optimize the addressing expression, do so now.
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if (OptimizeAddress(MI, 0))
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return true;
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break;
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case X86::MOVmr32:
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case X86::MOVmr16:
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case X86::MOVmr8:
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// If we can optimize the addressing expression, do so now.
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if (OptimizeAddress(MI, 1))
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return true;
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break;
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default: break;
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}
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return Changed;
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}
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