Matt Arsenault 2220408e1a Support REG_SEQUENCE in tablegen. ... The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221117 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-02 23:46:51 +00:00
..
Analysis	IR: MDNode => Value: Instruction::getMetadata()	2014-11-01 00:10:31 +00:00
AsmParser
Bitcode	Remove redundant calls to isMaterializable.	2014-11-01 16:46:18 +00:00
CodeGen	Formatting	2014-11-02 08:52:37 +00:00
DebugInfo
ExecutionEngine	[JIT] Fix some more missing endian conversions in RuntimeDyld	2014-11-01 15:52:31 +00:00
IR	Remove redundant calls to isMaterializable.	2014-11-01 16:46:18 +00:00
IRReader
LineEditor
Linker	Revert r221096 bringing back r221014 with a fix.	2014-11-02 13:28:57 +00:00
LTO
MC
Object
Option
ProfileData	Add show and merge tools for sample PGO profiles.	2014-11-01 00:56:55 +00:00
Support	Update the non-pthreads fallback for RWMutex on Unix	2014-10-31 17:02:30 +00:00
TableGen
Target	Support REG_SEQUENCE in tablegen.	2014-11-02 23:46:51 +00:00
Transforms	Use Alias Analysis to hoist 2 loads from diamond to the common predecessor basic block.	2014-11-02 08:03:05 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile