Ahmed Bougacha 75da31ff15 [AArch64] Keep flags on condition vreg when instantiating a CB branch. ...

Reversing a CB* instruction used to drop the flags on the condition. On the
included testcase, this lead to a read from an undefined vreg.
Using addOperand keeps the flags, here <undef>.

Differential Revision: http://reviews.llvm.org/D6159


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221507 91177308-0d34-0410-b5e6-96231b3b80d8

2014-11-07 02:50:00 +00:00

..

AArch64

[AArch64] Keep flags on condition vreg when instantiating a CB branch.

2014-11-07 02:50:00 +00:00

ARM

[RegAlloc] Remove reference to the trivial spiller in test case.

2014-11-06 19:24:18 +00:00

CPP

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Generic

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Hexagon

Handle ctor/init_array initialization.

2014-11-03 14:56:05 +00:00

Inputs

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Mips

[mips] Tolerate the use of the %z inline asm operand modifier with non-immediates.

2014-11-06 14:25:42 +00:00

MSP430

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NVPTX

[NVPTX] Add NVPTXLowerStructArgs pass

2014-11-05 18:19:30 +00:00

PowerPC

[PowerPC] Initial VSX intrinsic support, with min/max for vector double

2014-10-31 19:19:07 +00:00

R600

R600/SI: Add testcase I forgot to commit from months ago

2014-11-05 19:01:22 +00:00

SPARC

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SystemZ

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Thumb

Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.

2014-11-05 06:43:02 +00:00

Thumb2

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X86

[X86][SSE] Vector integer/float conversion memory folding (cvttps2dq / cvttpd2dq)

2014-11-06 22:15:41 +00:00

XCore

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