mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-06 21:05:51 +00:00
7cb1b5f5bf
llc using the host cpu features and *waning* on unknown features is probably not a good thing :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
3.4 KiB
LLVM
156 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx < %s | FileCheck %s --check-prefix SSE41
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx,-avx2 < %s | FileCheck %s --check-prefix AVX
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define i32 @veccond128(<4 x i32> %input) {
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block: ; preds = %entry
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ret i32 0
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endif-block: ; preds = %entry,
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ret i32 1
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; SSE41: veccond128
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; SSE41: ptest
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; SSE41: ret
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; AVX: veccond128
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; AVX: vptest %xmm{{.*}}, %xmm{{.*}}
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; AVX: ret
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}
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define i32 @veccond256(<8 x i32> %input) {
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entry:
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%0 = bitcast <8 x i32> %input to i256
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%1 = icmp ne i256 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block: ; preds = %entry
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ret i32 0
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endif-block: ; preds = %entry,
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ret i32 1
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; SSE41: veccond256
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; SSE41: por
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; SSE41: ptest
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; SSE41: ret
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; AVX: veccond256
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; AVX: vptest %ymm{{.*}}, %ymm{{.*}}
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; AVX: ret
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}
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define i32 @veccond512(<16 x i32> %input) {
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entry:
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%0 = bitcast <16 x i32> %input to i512
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%1 = icmp ne i512 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block: ; preds = %entry
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ret i32 0
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endif-block: ; preds = %entry,
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ret i32 1
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; SSE41: veccond512
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; SSE41: por
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; SSE41: por
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; SSE41: por
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; SSE41: ptest
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; SSE41: ret
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; AVX: veccond512
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; AVX: vorps
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; AVX: vptest %ymm{{.*}}, %ymm{{.*}}
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; AVX: ret
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}
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define i32 @vectest128(<4 x i32> %input) {
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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; SSE41: vectest128
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; SSE41: ptest
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; SSE41: ret
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; AVX: vectest128
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; AVX: vptest %xmm{{.*}}, %xmm{{.*}}
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; AVX: ret
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}
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define i32 @vectest256(<8 x i32> %input) {
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entry:
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%0 = bitcast <8 x i32> %input to i256
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%1 = icmp ne i256 %0, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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; SSE41: vectest256
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; SSE41: por
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; SSE41: ptest
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; SSE41: ret
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; AVX: vectest256
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; AVX: vptest %ymm{{.*}}, %ymm{{.*}}
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; AVX: ret
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}
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define i32 @vectest512(<16 x i32> %input) {
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entry:
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%0 = bitcast <16 x i32> %input to i512
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%1 = icmp ne i512 %0, 0
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%2 = zext i1 %1 to i32
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ret i32 %2
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; SSE41: vectest512
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; SSE41: por
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; SSE41: por
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; SSE41: por
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; SSE41: ptest
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; SSE41: ret
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; AVX: vectest512
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; AVX: vorps
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; AVX: vptest %ymm{{.*}}, %ymm{{.*}}
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; AVX: ret
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}
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define i32 @vecsel128(<4 x i32> %input, i32 %a, i32 %b) {
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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%2 = select i1 %1, i32 %a, i32 %b
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ret i32 %2
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; SSE41: vecsel128
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; SSE41: ptest
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; SSE41: ret
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; AVX: vecsel128
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; AVX: vptest %xmm{{.*}}, %xmm{{.*}}
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; AVX: ret
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}
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define i32 @vecsel256(<8 x i32> %input, i32 %a, i32 %b) {
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entry:
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%0 = bitcast <8 x i32> %input to i256
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%1 = icmp ne i256 %0, 0
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%2 = select i1 %1, i32 %a, i32 %b
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ret i32 %2
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; SSE41: vecsel256
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; SSE41: por
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; SSE41: ptest
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; SSE41: ret
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; AVX: vecsel256
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; AVX: vptest %ymm{{.*}}, %ymm{{.*}}
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; AVX: ret
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}
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define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) {
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entry:
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%0 = bitcast <16 x i32> %input to i512
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%1 = icmp ne i512 %0, 0
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%2 = select i1 %1, i32 %a, i32 %b
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ret i32 %2
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; SSE41: vecsel512
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; SSE41: por
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; SSE41: por
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; SSE41: por
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; SSE41: ptest
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; SSE41: ret
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; AVX: vecsel512
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; AVX: vorps
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; AVX: vptest %ymm{{.*}}, %ymm{{.*}}
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; AVX: ret
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}
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