mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
Includes a fix for a horrible typo that caused all SDIV costs to be slightly off :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207371 91177308-0d34-0410-b5e6-96231b3b80d8
1020 lines
38 KiB
C++
1020 lines
38 KiB
C++
//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// X86 target machine. It uses the target's detailed information to provide
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/// more precise answers to certain TTI queries, while letting the target
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/// independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86tti"
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// Declare the pass initialization routine locally as target-specific passes
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// don't havve a target-wide initialization entry point, and so we rely on the
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// pass constructor initialization.
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namespace llvm {
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void initializeX86TTIPass(PassRegistry &);
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}
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static cl::opt<bool>
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UsePartialUnrolling("x86-use-partial-unrolling", cl::init(true),
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cl::desc("Use partial unrolling for some X86 targets"), cl::Hidden);
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static cl::opt<unsigned>
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PartialUnrollingThreshold("x86-partial-unrolling-threshold", cl::init(0),
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cl::desc("Threshold for X86 partial unrolling"), cl::Hidden);
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static cl::opt<unsigned>
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PartialUnrollingMaxBranches("x86-partial-max-branches", cl::init(2),
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cl::desc("Threshold for taken branches in X86 partial unrolling"),
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cl::Hidden);
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namespace {
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class X86TTI final : public ImmutablePass, public TargetTransformInfo {
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const X86Subtarget *ST;
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const X86TargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
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public:
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X86TTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
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llvm_unreachable("This pass cannot be directly constructed");
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}
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X86TTI(const X86TargetMachine *TM)
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: ImmutablePass(ID), ST(TM->getSubtargetImpl()),
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TLI(TM->getTargetLowering()) {
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initializeX86TTIPass(*PassRegistry::getPassRegistry());
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}
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void initializePass() override {
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pushTTIStack(this);
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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TargetTransformInfo::getAnalysisUsage(AU);
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}
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/// Pass identification.
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static char ID;
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/// Provide necessary pointer adjustments for the two base classes.
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void *getAdjustedAnalysisPointer(const void *ID) override {
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if (ID == &TargetTransformInfo::ID)
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return (TargetTransformInfo*)this;
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return this;
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}
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/// \name Scalar TTI Implementations
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/// @{
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PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
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void getUnrollingPreferences(Loop *L,
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UnrollingPreferences &UP) const override;
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector) const override;
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unsigned getRegisterBitWidth(bool Vector) const override;
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unsigned getMaximumUnrollFactor() const override;
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unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind,
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OperandValueKind) const override;
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unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
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int Index, Type *SubTp) const override;
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) const override;
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) const override;
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) const override;
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unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace) const override;
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unsigned getAddressComputationCost(Type *PtrTy,
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bool IsComplex) const override;
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unsigned getReductionCost(unsigned Opcode, Type *Ty,
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bool IsPairwiseForm) const override;
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unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
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unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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Type *Ty) const override;
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unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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Type *Ty) const override;
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/// @}
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};
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} // end anonymous namespace
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INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
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"X86 Target Transform Info", true, true, false)
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char X86TTI::ID = 0;
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ImmutablePass *
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llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
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return new X86TTI(TM);
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}
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//===----------------------------------------------------------------------===//
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//
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// X86 cost model.
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//
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//===----------------------------------------------------------------------===//
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X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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// TODO: Currently the __builtin_popcount() implementation using SSE3
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// instructions is inefficient. Once the problem is fixed, we should
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// call ST->hasSSE3() instead of ST->hasPOPCNT().
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return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
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}
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void X86TTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
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if (!UsePartialUnrolling)
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return;
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// According to the Intel 64 and IA-32 Architectures Optimization Reference
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// Manual, Intel Core models and later have a loop stream detector
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// (and associated uop queue) that can benefit from partial unrolling.
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// The relevant requirements are:
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// - The loop must have no more than 4 (8 for Nehalem and later) branches
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// taken, and none of them may be calls.
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// - The loop can have no more than 18 (28 for Nehalem and later) uops.
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// According to the Software Optimization Guide for AMD Family 15h Processors,
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// models 30h-4fh (Steamroller and later) have a loop predictor and loop
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// buffer which can benefit from partial unrolling.
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// The relevant requirements are:
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// - The loop must have fewer than 16 branches
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// - The loop must have less than 40 uops in all executed loop branches
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unsigned MaxBranches, MaxOps;
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if (PartialUnrollingThreshold.getNumOccurrences() > 0) {
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MaxBranches = PartialUnrollingMaxBranches;
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MaxOps = PartialUnrollingThreshold;
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} else if (ST->isAtom()) {
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// On the Atom, the throughput for taken branches is 2 cycles. For small
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// simple loops, expand by a small factor to hide the backedge cost.
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MaxBranches = 2;
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MaxOps = 10;
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} else if (ST->hasFSGSBase() && ST->hasXOP() /* Steamroller and later */) {
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MaxBranches = 16;
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MaxOps = 40;
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} else if (ST->hasFMA4() /* Any other recent AMD */) {
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return;
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} else if (ST->hasAVX() || ST->hasSSE42() /* Nehalem and later */) {
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MaxBranches = 8;
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MaxOps = 28;
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} else if (ST->hasSSSE3() /* Intel Core */) {
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MaxBranches = 4;
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MaxOps = 18;
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} else {
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return;
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}
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// Scan the loop: don't unroll loops with calls, and count the potential
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// number of taken branches (this is somewhat conservative because we're
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// counting all block transitions as potential branches while in reality some
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// of these will become implicit via block placement).
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unsigned MaxDepth = 0;
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for (df_iterator<BasicBlock*> DI = df_begin(L->getHeader()),
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DE = df_end(L->getHeader()); DI != DE;) {
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if (!L->contains(*DI)) {
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DI.skipChildren();
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continue;
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}
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MaxDepth = std::max(MaxDepth, DI.getPathLength());
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if (MaxDepth > MaxBranches)
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return;
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for (BasicBlock::iterator I = DI->begin(), IE = DI->end(); I != IE; ++I)
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if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
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ImmutableCallSite CS(I);
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if (const Function *F = CS.getCalledFunction()) {
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if (!isLoweredToCall(F))
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continue;
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}
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return;
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}
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++DI;
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}
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// Enable runtime and partial unrolling up to the specified size.
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UP.Partial = UP.Runtime = true;
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UP.PartialThreshold = UP.PartialOptSizeThreshold = MaxOps;
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// Set the maximum count based on the loop depth. The maximum number of
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// branches taken in a loop (including the backedge) is equal to the maximum
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// loop depth (the DFS path length from the loop header to any block in the
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// loop). When the loop is unrolled, this depth (except for the backedge
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// itself) is multiplied by the unrolling factor. This new unrolled depth
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// must be less than the target-specific maximum branch count (which limits
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// the number of taken branches in the uop buffer).
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if (MaxDepth > 1)
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UP.MaxCount = (MaxBranches-1)/(MaxDepth-1);
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}
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unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
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if (Vector && !ST->hasSSE1())
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return 0;
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if (ST->is64Bit())
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return 16;
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return 8;
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}
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unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
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if (Vector) {
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if (ST->hasAVX()) return 256;
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if (ST->hasSSE1()) return 128;
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return 0;
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}
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if (ST->is64Bit())
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return 64;
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return 32;
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}
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unsigned X86TTI::getMaximumUnrollFactor() const {
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if (ST->isAtom())
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return 1;
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// Sandybridge and Haswell have multiple execution ports and pipelined
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// vector units.
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if (ST->hasAVX())
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return 4;
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return 2;
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}
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unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
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OperandValueKind Op1Info,
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OperandValueKind Op2Info) const {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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static const CostTblEntry<MVT::SimpleValueType>
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AVX2UniformConstCostTable[] = {
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{ ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
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{ ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
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{ ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
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{ ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
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};
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if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
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ST->hasAVX2()) {
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int Idx = CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * AVX2UniformConstCostTable[Idx].Cost;
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}
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static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
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// Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
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// customize them to detect the cases where shift amount is a scalar one.
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{ ISD::SHL, MVT::v4i32, 1 },
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{ ISD::SRL, MVT::v4i32, 1 },
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{ ISD::SRA, MVT::v4i32, 1 },
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{ ISD::SHL, MVT::v8i32, 1 },
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{ ISD::SRL, MVT::v8i32, 1 },
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{ ISD::SRA, MVT::v8i32, 1 },
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{ ISD::SHL, MVT::v2i64, 1 },
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{ ISD::SRL, MVT::v2i64, 1 },
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{ ISD::SHL, MVT::v4i64, 1 },
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{ ISD::SRL, MVT::v4i64, 1 },
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{ ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
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{ ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
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{ ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
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{ ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
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{ ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
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{ ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
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{ ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
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// Vectorizing division is a bad idea. See the SSE2 table for more comments.
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{ ISD::SDIV, MVT::v32i8, 32*20 },
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{ ISD::SDIV, MVT::v16i16, 16*20 },
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{ ISD::SDIV, MVT::v8i32, 8*20 },
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{ ISD::SDIV, MVT::v4i64, 4*20 },
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{ ISD::UDIV, MVT::v32i8, 32*20 },
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{ ISD::UDIV, MVT::v16i16, 16*20 },
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{ ISD::UDIV, MVT::v8i32, 8*20 },
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{ ISD::UDIV, MVT::v4i64, 4*20 },
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};
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// Look for AVX2 lowering tricks.
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if (ST->hasAVX2()) {
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if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
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(Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
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Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
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// On AVX2, a packed v16i16 shift left by a constant build_vector
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// is lowered into a vector multiply (vpmullw).
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return LT.first;
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int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * AVX2CostTable[Idx].Cost;
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}
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static const CostTblEntry<MVT::SimpleValueType>
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SSE2UniformConstCostTable[] = {
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// We don't correctly identify costs of casts because they are marked as
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// custom.
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// Constant splats are cheaper for the following instructions.
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{ ISD::SHL, MVT::v16i8, 1 }, // psllw.
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{ ISD::SHL, MVT::v8i16, 1 }, // psllw.
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{ ISD::SHL, MVT::v4i32, 1 }, // pslld
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{ ISD::SHL, MVT::v2i64, 1 }, // psllq.
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{ ISD::SRL, MVT::v16i8, 1 }, // psrlw.
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{ ISD::SRL, MVT::v8i16, 1 }, // psrlw.
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{ ISD::SRL, MVT::v4i32, 1 }, // psrld.
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{ ISD::SRL, MVT::v2i64, 1 }, // psrlq.
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{ ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
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{ ISD::SRA, MVT::v8i16, 1 }, // psraw.
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{ ISD::SRA, MVT::v4i32, 1 }, // psrad.
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{ ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
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{ ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
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{ ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
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{ ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
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};
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if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
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ST->hasSSE2()) {
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// pmuldq sequence.
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if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
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return LT.first * 15;
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int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
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if (Idx != -1)
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return LT.first * SSE2UniformConstCostTable[Idx].Cost;
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}
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if (ISD == ISD::SHL &&
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Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
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EVT VT = LT.second;
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if ((VT == MVT::v8i16 && ST->hasSSE2()) ||
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(VT == MVT::v4i32 && ST->hasSSE41()))
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// Vector shift left by non uniform constant can be lowered
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// into vector multiply (pmullw/pmulld).
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return LT.first;
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if (VT == MVT::v4i32 && ST->hasSSE2())
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// A vector shift left by non uniform constant is converted
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// into a vector multiply; the new multiply is eventually
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// lowered into a sequence of shuffles and 2 x pmuludq.
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ISD = ISD::MUL;
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}
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static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
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// We don't correctly identify costs of casts because they are marked as
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// custom.
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// For some cases, where the shift amount is a scalar we would be able
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// to generate better code. Unfortunately, when this is the case the value
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// (the splat) will get hoisted out of the loop, thereby making it invisible
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// to ISel. The cost model must return worst case assumptions because it is
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// used for vectorization and we don't want to make vectorized code worse
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// than scalar code.
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{ ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
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{ ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
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{ ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
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{ ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
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{ ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
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{ ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
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{ ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
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{ ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
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{ ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
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{ ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
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{ ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
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{ ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
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{ ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
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// It is not a good idea to vectorize division. We have to scalarize it and
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// in the process we will often end up having to spilling regular
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// registers. The overhead of division is going to dominate most kernels
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// anyways so try hard to prevent vectorization of division - it is
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// generally a bad idea. Assume somewhat arbitrarily that we have to be able
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// to hide "20 cycles" for each lane.
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{ ISD::SDIV, MVT::v16i8, 16*20 },
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{ ISD::SDIV, MVT::v8i16, 8*20 },
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{ ISD::SDIV, MVT::v4i32, 4*20 },
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{ ISD::SDIV, MVT::v2i64, 2*20 },
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{ ISD::UDIV, MVT::v16i8, 16*20 },
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{ ISD::UDIV, MVT::v8i16, 8*20 },
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{ ISD::UDIV, MVT::v4i32, 4*20 },
|
|
{ ISD::UDIV, MVT::v2i64, 2*20 },
|
|
};
|
|
|
|
if (ST->hasSSE2()) {
|
|
int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
|
|
if (Idx != -1)
|
|
return LT.first * SSE2CostTable[Idx].Cost;
|
|
}
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
|
|
// We don't have to scalarize unsupported ops. We can issue two half-sized
|
|
// operations and we only need to extract the upper YMM half.
|
|
// Two ops + 1 extract + 1 insert = 4.
|
|
{ ISD::MUL, MVT::v16i16, 4 },
|
|
{ ISD::MUL, MVT::v8i32, 4 },
|
|
{ ISD::SUB, MVT::v8i32, 4 },
|
|
{ ISD::ADD, MVT::v8i32, 4 },
|
|
{ ISD::SUB, MVT::v4i64, 4 },
|
|
{ ISD::ADD, MVT::v4i64, 4 },
|
|
// A v4i64 multiply is custom lowered as two split v2i64 vectors that then
|
|
// are lowered as a series of long multiplies(3), shifts(4) and adds(2)
|
|
// Because we believe v4i64 to be a legal type, we must also include the
|
|
// split factor of two in the cost table. Therefore, the cost here is 18
|
|
// instead of 9.
|
|
{ ISD::MUL, MVT::v4i64, 18 },
|
|
};
|
|
|
|
// Look for AVX1 lowering tricks.
|
|
if (ST->hasAVX() && !ST->hasAVX2()) {
|
|
EVT VT = LT.second;
|
|
|
|
// v16i16 and v8i32 shifts by non-uniform constants are lowered into a
|
|
// sequence of extract + two vector multiply + insert.
|
|
if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
|
|
Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)
|
|
ISD = ISD::MUL;
|
|
|
|
int Idx = CostTableLookup(AVX1CostTable, ISD, VT);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTable[Idx].Cost;
|
|
}
|
|
|
|
// Custom lowering of vectors.
|
|
static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
|
|
// A v2i64/v4i64 and multiply is custom lowered as a series of long
|
|
// multiplies(3), shifts(4) and adds(2).
|
|
{ ISD::MUL, MVT::v2i64, 9 },
|
|
{ ISD::MUL, MVT::v4i64, 9 },
|
|
};
|
|
int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
|
|
if (Idx != -1)
|
|
return LT.first * CustomLowered[Idx].Cost;
|
|
|
|
// Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
|
|
// 2x pmuludq, 2x shuffle.
|
|
if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
|
|
!ST->hasSSE41())
|
|
return LT.first * 6;
|
|
|
|
// Fallback to the default implementation.
|
|
return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
|
|
Op2Info);
|
|
}
|
|
|
|
unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
|
|
Type *SubTp) const {
|
|
// We only estimate the cost of reverse shuffles.
|
|
if (Kind != SK_Reverse)
|
|
return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
|
|
unsigned Cost = 1;
|
|
if (LT.second.getSizeInBits() > 128)
|
|
Cost = 3; // Extract + insert + copy.
|
|
|
|
// Multiple by the number of parts.
|
|
return Cost * LT.first;
|
|
}
|
|
|
|
unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
assert(ISD && "Invalid opcode");
|
|
|
|
std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
|
|
std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
|
|
|
|
static const TypeConversionCostTblEntry<MVT::SimpleValueType>
|
|
SSE2ConvTbl[] = {
|
|
// These are somewhat magic numbers justified by looking at the output of
|
|
// Intel's IACA, running some kernels and making sure when we take
|
|
// legalization into account the throughput will be overestimated.
|
|
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
|
|
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
|
|
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
|
|
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
|
|
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
|
|
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
|
|
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
|
|
{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
|
|
// There are faster sequences for float conversions.
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
|
|
};
|
|
|
|
if (ST->hasSSE2() && !ST->hasAVX()) {
|
|
int Idx =
|
|
ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
|
|
if (Idx != -1)
|
|
return LTSrc.first * SSE2ConvTbl[Idx].Cost;
|
|
}
|
|
|
|
EVT SrcTy = TLI->getValueType(Src);
|
|
EVT DstTy = TLI->getValueType(Dst);
|
|
|
|
// The function getSimpleVT only handles simple value types.
|
|
if (!SrcTy.isSimple() || !DstTy.isSimple())
|
|
return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
|
|
|
|
static const TypeConversionCostTblEntry<MVT::SimpleValueType>
|
|
AVX2ConversionTbl[] = {
|
|
{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
|
|
{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
|
|
|
|
{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
|
|
{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
|
|
{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
|
|
{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
|
|
{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
|
|
{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
|
|
};
|
|
|
|
static const TypeConversionCostTblEntry<MVT::SimpleValueType>
|
|
AVXConversionTbl[] = {
|
|
{ ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
|
|
{ ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
|
|
{ ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
|
|
{ ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
|
|
{ ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
|
|
{ ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
|
|
|
|
{ ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
|
|
{ ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
|
|
{ ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
|
|
{ ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
|
|
{ ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
|
|
{ ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
|
|
{ ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
|
|
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
|
|
{ ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
|
|
{ ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
|
|
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
|
|
{ ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
|
|
// The generic code to compute the scalar overhead is currently broken.
|
|
// Workaround this limitation by estimating the scalarization overhead
|
|
// here. We have roughly 10 instructions per scalar element.
|
|
// Multiply that by the vector width.
|
|
// FIXME: remove that when PR19268 is fixed.
|
|
{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
|
|
{ ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 4*10 },
|
|
|
|
{ ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
|
|
{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
|
|
// This node is expanded into scalarized operations but BasicTTI is overly
|
|
// optimistic estimating its cost. It computes 3 per element (one
|
|
// vector-extract, one scalar conversion and one vector-insert). The
|
|
// problem is that the inserts form a read-modify-write chain so latency
|
|
// should be factored in too. Inflating the cost per element by 1.
|
|
{ ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
|
|
{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
|
|
};
|
|
|
|
if (ST->hasAVX2()) {
|
|
int Idx = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
|
|
DstTy.getSimpleVT(), SrcTy.getSimpleVT());
|
|
if (Idx != -1)
|
|
return AVX2ConversionTbl[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasAVX()) {
|
|
int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
|
|
SrcTy.getSimpleVT());
|
|
if (Idx != -1)
|
|
return AVXConversionTbl[Idx].Cost;
|
|
}
|
|
|
|
return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
|
|
}
|
|
|
|
unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
|
|
Type *CondTy) const {
|
|
// Legalize the type.
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
|
|
|
|
MVT MTy = LT.second;
|
|
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
assert(ISD && "Invalid opcode");
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
|
|
{ ISD::SETCC, MVT::v2f64, 1 },
|
|
{ ISD::SETCC, MVT::v4f32, 1 },
|
|
{ ISD::SETCC, MVT::v2i64, 1 },
|
|
{ ISD::SETCC, MVT::v4i32, 1 },
|
|
{ ISD::SETCC, MVT::v8i16, 1 },
|
|
{ ISD::SETCC, MVT::v16i8, 1 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
|
|
{ ISD::SETCC, MVT::v4f64, 1 },
|
|
{ ISD::SETCC, MVT::v8f32, 1 },
|
|
// AVX1 does not support 8-wide integer compare.
|
|
{ ISD::SETCC, MVT::v4i64, 4 },
|
|
{ ISD::SETCC, MVT::v8i32, 4 },
|
|
{ ISD::SETCC, MVT::v16i16, 4 },
|
|
{ ISD::SETCC, MVT::v32i8, 4 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
|
|
{ ISD::SETCC, MVT::v4i64, 1 },
|
|
{ ISD::SETCC, MVT::v8i32, 1 },
|
|
{ ISD::SETCC, MVT::v16i16, 1 },
|
|
{ ISD::SETCC, MVT::v32i8, 1 },
|
|
};
|
|
|
|
if (ST->hasAVX2()) {
|
|
int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX2CostTbl[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasAVX()) {
|
|
int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTbl[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasSSE42()) {
|
|
int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * SSE42CostTbl[Idx].Cost;
|
|
}
|
|
|
|
return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
|
|
}
|
|
|
|
unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
|
|
unsigned Index) const {
|
|
assert(Val->isVectorTy() && "This must be a vector type");
|
|
|
|
if (Index != -1U) {
|
|
// Legalize the type.
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
|
|
|
|
// This type is legalized to a scalar type.
|
|
if (!LT.second.isVector())
|
|
return 0;
|
|
|
|
// The type may be split. Normalize the index to the new type.
|
|
unsigned Width = LT.second.getVectorNumElements();
|
|
Index = Index % Width;
|
|
|
|
// Floating point scalars are already located in index #0.
|
|
if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
|
|
return 0;
|
|
}
|
|
|
|
return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
|
|
}
|
|
|
|
unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
|
|
bool Extract) const {
|
|
assert (Ty->isVectorTy() && "Can only scalarize vectors");
|
|
unsigned Cost = 0;
|
|
|
|
for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
|
|
if (Insert)
|
|
Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
|
|
if (Extract)
|
|
Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
|
|
}
|
|
|
|
return Cost;
|
|
}
|
|
|
|
unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
|
unsigned AddressSpace) const {
|
|
// Handle non-power-of-two vectors such as <3 x float>
|
|
if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
|
|
unsigned NumElem = VTy->getVectorNumElements();
|
|
|
|
// Handle a few common cases:
|
|
// <3 x float>
|
|
if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
|
|
// Cost = 64 bit store + extract + 32 bit store.
|
|
return 3;
|
|
|
|
// <3 x double>
|
|
if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
|
|
// Cost = 128 bit store + unpack + 64 bit store.
|
|
return 3;
|
|
|
|
// Assume that all other non-power-of-two numbers are scalarized.
|
|
if (!isPowerOf2_32(NumElem)) {
|
|
unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
|
|
VTy->getScalarType(),
|
|
Alignment,
|
|
AddressSpace);
|
|
unsigned SplitCost = getScalarizationOverhead(Src,
|
|
Opcode == Instruction::Load,
|
|
Opcode==Instruction::Store);
|
|
return NumElem * Cost + SplitCost;
|
|
}
|
|
}
|
|
|
|
// Legalize the type.
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
|
|
assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
|
|
"Invalid Opcode");
|
|
|
|
// Each load/store unit costs 1.
|
|
unsigned Cost = LT.first * 1;
|
|
|
|
// On Sandybridge 256bit load/stores are double pumped
|
|
// (but not on Haswell).
|
|
if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
|
|
Cost*=2;
|
|
|
|
return Cost;
|
|
}
|
|
|
|
unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
|
|
// Address computations in vectorized code with non-consecutive addresses will
|
|
// likely result in more instructions compared to scalar code where the
|
|
// computation can more often be merged into the index mode. The resulting
|
|
// extra micro-ops can significantly decrease throughput.
|
|
unsigned NumVectorInstToHideOverhead = 10;
|
|
|
|
if (Ty->isVectorTy() && IsComplex)
|
|
return NumVectorInstToHideOverhead;
|
|
|
|
return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
|
|
}
|
|
|
|
unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
|
|
bool IsPairwise) const {
|
|
|
|
std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
|
|
|
|
MVT MTy = LT.second;
|
|
|
|
int ISD = TLI->InstructionOpcodeToISD(Opcode);
|
|
assert(ISD && "Invalid opcode");
|
|
|
|
// We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
|
|
// and make it as the cost.
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
|
|
{ ISD::FADD, MVT::v2f64, 2 },
|
|
{ ISD::FADD, MVT::v4f32, 4 },
|
|
{ ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
|
|
{ ISD::ADD, MVT::v8i16, 5 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
|
|
{ ISD::FADD, MVT::v4f32, 4 },
|
|
{ ISD::FADD, MVT::v4f64, 5 },
|
|
{ ISD::FADD, MVT::v8f32, 7 },
|
|
{ ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
|
|
{ ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
|
|
{ ISD::ADD, MVT::v8i16, 5 },
|
|
{ ISD::ADD, MVT::v8i32, 5 },
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
|
|
{ ISD::FADD, MVT::v2f64, 2 },
|
|
{ ISD::FADD, MVT::v4f32, 4 },
|
|
{ ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
|
|
{ ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
|
|
};
|
|
|
|
static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
|
|
{ ISD::FADD, MVT::v4f32, 3 },
|
|
{ ISD::FADD, MVT::v4f64, 3 },
|
|
{ ISD::FADD, MVT::v8f32, 4 },
|
|
{ ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
|
|
{ ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
|
|
{ ISD::ADD, MVT::v4i64, 3 },
|
|
{ ISD::ADD, MVT::v8i16, 4 },
|
|
{ ISD::ADD, MVT::v8i32, 5 },
|
|
};
|
|
|
|
if (IsPairwise) {
|
|
if (ST->hasAVX()) {
|
|
int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTblPairWise[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasSSE42()) {
|
|
int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * SSE42CostTblPairWise[Idx].Cost;
|
|
}
|
|
} else {
|
|
if (ST->hasAVX()) {
|
|
int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
|
|
}
|
|
|
|
if (ST->hasSSE42()) {
|
|
int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
|
|
if (Idx != -1)
|
|
return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
|
|
}
|
|
}
|
|
|
|
return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);
|
|
}
|
|
|
|
unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
|
|
assert(Ty->isIntegerTy());
|
|
|
|
unsigned BitSize = Ty->getPrimitiveSizeInBits();
|
|
if (BitSize == 0)
|
|
return ~0U;
|
|
|
|
if (Imm == 0)
|
|
return TCC_Free;
|
|
|
|
if (Imm.getBitWidth() <= 64 &&
|
|
(isInt<32>(Imm.getSExtValue()) || isUInt<32>(Imm.getZExtValue())))
|
|
return TCC_Basic;
|
|
else
|
|
return 2 * TCC_Basic;
|
|
}
|
|
|
|
unsigned X86TTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
|
|
Type *Ty) const {
|
|
assert(Ty->isIntegerTy());
|
|
|
|
unsigned BitSize = Ty->getPrimitiveSizeInBits();
|
|
if (BitSize == 0)
|
|
return ~0U;
|
|
|
|
unsigned ImmIdx = ~0U;
|
|
switch (Opcode) {
|
|
default: return TCC_Free;
|
|
case Instruction::GetElementPtr:
|
|
// Always hoist the base address of a GetElementPtr. This prevents the
|
|
// creation of new constants for every base constant that gets constant
|
|
// folded with the offset.
|
|
if (Idx == 0)
|
|
return 2 * TCC_Basic;
|
|
return TCC_Free;
|
|
case Instruction::Store:
|
|
ImmIdx = 0;
|
|
break;
|
|
case Instruction::Add:
|
|
case Instruction::Sub:
|
|
case Instruction::Mul:
|
|
case Instruction::UDiv:
|
|
case Instruction::SDiv:
|
|
case Instruction::URem:
|
|
case Instruction::SRem:
|
|
case Instruction::Shl:
|
|
case Instruction::LShr:
|
|
case Instruction::AShr:
|
|
case Instruction::And:
|
|
case Instruction::Or:
|
|
case Instruction::Xor:
|
|
case Instruction::ICmp:
|
|
ImmIdx = 1;
|
|
break;
|
|
case Instruction::Trunc:
|
|
case Instruction::ZExt:
|
|
case Instruction::SExt:
|
|
case Instruction::IntToPtr:
|
|
case Instruction::PtrToInt:
|
|
case Instruction::BitCast:
|
|
case Instruction::PHI:
|
|
case Instruction::Call:
|
|
case Instruction::Select:
|
|
case Instruction::Ret:
|
|
case Instruction::Load:
|
|
break;
|
|
}
|
|
|
|
if ((Idx == ImmIdx) &&
|
|
Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
|
|
return TCC_Free;
|
|
|
|
return X86TTI::getIntImmCost(Imm, Ty);
|
|
}
|
|
|
|
unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
|
|
const APInt &Imm, Type *Ty) const {
|
|
assert(Ty->isIntegerTy());
|
|
|
|
unsigned BitSize = Ty->getPrimitiveSizeInBits();
|
|
if (BitSize == 0)
|
|
return ~0U;
|
|
|
|
switch (IID) {
|
|
default: return TCC_Free;
|
|
case Intrinsic::sadd_with_overflow:
|
|
case Intrinsic::uadd_with_overflow:
|
|
case Intrinsic::ssub_with_overflow:
|
|
case Intrinsic::usub_with_overflow:
|
|
case Intrinsic::smul_with_overflow:
|
|
case Intrinsic::umul_with_overflow:
|
|
if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
|
|
return TCC_Free;
|
|
break;
|
|
case Intrinsic::experimental_stackmap:
|
|
if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
|
|
return TCC_Free;
|
|
break;
|
|
case Intrinsic::experimental_patchpoint_void:
|
|
case Intrinsic::experimental_patchpoint_i64:
|
|
if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
|
|
return TCC_Free;
|
|
break;
|
|
}
|
|
return X86TTI::getIntImmCost(Imm, Ty);
|
|
}
|