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These objects are internal to the TargetMachine object and may change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
173 lines
5.5 KiB
C++
173 lines
5.5 KiB
C++
//===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64RegisterInfo.h"
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#include "AArch64FrameLowering.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/ADT/BitVector.h"
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#define GET_REGINFO_TARGET_DESC
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#include "AArch64GenRegisterInfo.inc"
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using namespace llvm;
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AArch64RegisterInfo::AArch64RegisterInfo()
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: AArch64GenRegisterInfo(AArch64::X30) {
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}
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const uint16_t *
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AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_PCS_SaveList;
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}
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const uint32_t*
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AArch64RegisterInfo::getCallPreservedMask(CallingConv::ID) const {
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return CSR_PCS_RegMask;
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}
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const uint32_t *AArch64RegisterInfo::getTLSDescCallPreservedMask() const {
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return TLSDesc_RegMask;
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}
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const TargetRegisterClass *
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AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &AArch64::FlagClassRegClass)
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return &AArch64::GPR64RegClass;
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return RC;
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}
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BitVector
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AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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Reserved.set(AArch64::XSP);
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Reserved.set(AArch64::WSP);
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Reserved.set(AArch64::XZR);
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Reserved.set(AArch64::WZR);
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if (TFI->hasFP(MF)) {
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Reserved.set(AArch64::X29);
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Reserved.set(AArch64::W29);
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}
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return Reserved;
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}
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void
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AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MBBI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Cannot deal with nonzero SPAdj yet");
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const AArch64FrameLowering *TFI =
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static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering());
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// In order to work out the base and offset for addressing, the FrameLowering
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// code needs to know (sometimes) whether the instruction is storing/loading a
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// callee-saved register, or whether it's a more generic
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// operation. Fortunately the frame indices are used *only* for that purpose
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// and are contiguous, so we can check here.
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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int MinCSFI = 0;
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int MaxCSFI = -1;
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if (CSI.size()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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}
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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bool IsCalleeSaveOp = FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI;
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unsigned FrameReg;
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int64_t Offset;
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Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj,
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IsCalleeSaveOp);
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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// DBG_VALUE instructions have no real restrictions so they can be handled
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// easily.
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if (MI.isDebugValue()) {
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/ false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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return;
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}
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const AArch64InstrInfo &TII =
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*static_cast<const AArch64InstrInfo*>(MF.getTarget().getInstrInfo());
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int MinOffset, MaxOffset, OffsetScale;
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if (MI.getOpcode() == AArch64::ADDxxi_lsl0_s) {
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MinOffset = 0;
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MaxOffset = 0xfff;
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OffsetScale = 1;
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} else {
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// Load/store of a stack object
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TII.getAddressConstraints(MI, OffsetScale, MinOffset, MaxOffset);
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}
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// The frame lowering has told us a base and offset it thinks we should use to
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// access this variable, but it's still up to us to make sure the values are
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// legal for the instruction in question.
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if (Offset % OffsetScale != 0 || Offset < MinOffset || Offset > MaxOffset) {
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unsigned BaseReg =
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MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
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emitRegUpdate(MBB, MBBI, MBBI->getDebugLoc(), TII,
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BaseReg, FrameReg, BaseReg, Offset);
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FrameReg = BaseReg;
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Offset = 0;
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}
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// Negative offsets are expected if we address from FP, but for
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// now this checks nothing has gone horribly wrong.
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assert(Offset >= 0 && "Unexpected negative offset from SP");
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, true);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset / OffsetScale);
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}
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unsigned
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AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (TFI->hasFP(MF))
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return AArch64::X29;
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else
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return AArch64::XSP;
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}
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bool
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AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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const AArch64FrameLowering *AFI
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= static_cast<const AArch64FrameLowering*>(TFI);
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return AFI->useFPForAddressing(MF);
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}
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