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87d1836793
This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization). It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, that more closely matches the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner. Differential Revision: http://reviews.llvm.org/D9848 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237885 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| CMakeLists.txt | ||
| DAGCombiner.cpp | ||
| FastISel.cpp | ||
| FunctionLoweringInfo.cpp | ||
| InstrEmitter.cpp | ||
| InstrEmitter.h | ||
| LegalizeDAG.cpp | ||
| LegalizeFloatTypes.cpp | ||
| LegalizeIntegerTypes.cpp | ||
| LegalizeTypes.cpp | ||
| LegalizeTypes.h | ||
| LegalizeTypesGeneric.cpp | ||
| LegalizeVectorOps.cpp | ||
| LegalizeVectorTypes.cpp | ||
| LLVMBuild.txt | ||
| Makefile | ||
| ResourcePriorityQueue.cpp | ||
| ScheduleDAGFast.cpp | ||
| ScheduleDAGRRList.cpp | ||
| ScheduleDAGSDNodes.cpp | ||
| ScheduleDAGSDNodes.h | ||
| ScheduleDAGVLIW.cpp | ||
| SDNodeDbgValue.h | ||
| SelectionDAG.cpp | ||
| SelectionDAGBuilder.cpp | ||
| SelectionDAGBuilder.h | ||
| SelectionDAGDumper.cpp | ||
| SelectionDAGISel.cpp | ||
| SelectionDAGPrinter.cpp | ||
| StatepointLowering.cpp | ||
| StatepointLowering.h | ||
| TargetLowering.cpp | ||
| TargetSelectionDAGInfo.cpp | ||