Ulrich Weigand 1ef2cec146 Fix ppcf128 component access on little-endian systems ... The PowerPC 128-bit long double data type (ppcf128 in LLVM) is in fact a pair of two doubles, where one is considered the "high" or more-significant part, and the other is considered the "low" or less-significant part. When a ppcf128 value is stored in memory or a register pair, the high part always comes first, i.e. at the lower memory address or in the lower-numbered register, and the low part always comes second. This is true both on big-endian and little-endian PowerPC systems. (Similar to how with a complex number, the real part always comes first and the imaginary part second, no matter the byte order of the system.) This was implemented incorrectly for little-endian systems in LLVM. This commit fixes three related issues: - When printing an immediate ppcf128 constant to assembler output in emitGlobalConstantFP, emit the high part first on both big- and little-endian systems. - When lowering a ppcf128 type to a pair of f64 types in SelectionDAG (which is used e.g. when generating code to load an argument into a register pair), use correct low/high part ordering on little-endian systems. - In a related issue, because lowering ppcf128 into a pair of f64 must operate differently from lowering an int128 into a pair of i64, bitcasts between ppcf128 and int128 must not be optimized away by the DAG combiner on little-endian systems, but must effect a word-swap. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212274 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-03 15:06:47 +00:00
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CostTable.h	Add a overload to CostTable which allows it to infer the size of the table.	2013-08-09 19:33:32 +00:00
Target.td	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
TargetCallingConv.h	ARM: HFAs must be passed in consecutive registers	2014-05-09 14:01:47 +00:00
TargetCallingConv.td	ARM: HFAs must be passed in consecutive registers	2014-05-09 14:01:47 +00:00
TargetFrameLowering.h	Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter.	2014-06-25 12:41:52 +00:00
TargetInstrInfo.h	The hazard recognizer only needs a subtarget, not a target machine	2014-06-13 22:38:52 +00:00
TargetIntrinsicInfo.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-15 06:32:26 +00:00
TargetItinerary.td	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TargetJITInfo.h	Sort the #include lines for the include/... tree with the script.	2012-12-03 17:02:12 +00:00
TargetLibraryInfo.h	SimplifyLibCalls: Push TLI through the exp2->ldexp transform.	2014-02-04 20:27:23 +00:00
TargetLowering.h	Fix ppcf128 component access on little-endian systems	2014-07-03 15:06:47 +00:00
TargetLoweringObjectFile.h	Fix a few issues with comdat handling on COFF.	2014-06-06 19:26:12 +00:00
TargetMachine.h	Move the verbose asm option to be part of the options struct and	2014-05-20 23:59:50 +00:00
TargetOpcodes.h	Replace PROLOG_LABEL with a new CFI_INSTRUCTION.	2014-03-07 06:08:31 +00:00
TargetOptions.h	Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.	2014-06-05 19:29:43 +00:00
TargetRegisterInfo.h	[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.	2014-04-14 00:51:57 +00:00
TargetSchedule.td	Move late partial-unrolling thresholds into the processor definitions	2014-05-08 09:14:44 +00:00
TargetSelectionDAG.td	ARM64: initial backend import	2014-03-29 10:18:08 +00:00
TargetSelectionDAGInfo.h	Have TargetSelectionDAGInfo take a DataLayout initializer rather than	2014-06-06 19:04:48 +00:00
TargetSubtargetInfo.h	[RegAllocGreedy] Provide a subtarget hook to disable the local reassignment	2014-07-02 18:32:04 +00:00