Jim Grosbach e43862b6a6 ARM assembly parsing for register range syntax for VLD/VST register lists. ... For example, vld1.f64 {d2-d5}, [r2,:128]! Should be equivalent to: vld1.f64 {d2,d3,d4,d5}, [r2,:128]! It's not documented syntax in the ARM ARM, but it is consistent with what's accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to support. rdar://10451128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8		2011-11-15 23:19:15 +00:00
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ARM	ARM assembly parsing for register range syntax for VLD/VST register lists.	2011-11-15 23:19:15 +00:00
AsmParser	Move test to the X86 directory, note the PR number and only run MC once.	2011-10-31 17:23:09 +00:00
COFF
Disassembler	Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.	2011-11-15 19:55:00 +00:00
ELF
MachO	Fixed a bug in the code to create a dwarf file and directory table entires when	2011-11-01 23:39:05 +00:00
MBlaze
X86	Move test to the X86 directory, note the PR number and only run MC once.	2011-10-31 17:23:09 +00:00