mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
b5f662fa03
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
3.0 KiB
C++
79 lines
3.0 KiB
C++
//===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file was developed by the LLVM research group and is distributed under
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the PowerPC implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "PPC32InstrInfo.h"
|
|
#include "PPC32GenInstrInfo.inc"
|
|
#include "PowerPC.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include <iostream>
|
|
using namespace llvm;
|
|
|
|
PPC32InstrInfo::PPC32InstrInfo()
|
|
: TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {}
|
|
|
|
bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
|
|
unsigned& sourceReg,
|
|
unsigned& destReg) const {
|
|
MachineOpCode oc = MI.getOpcode();
|
|
if (oc == PPC::OR) { // or r1, r2, r2
|
|
assert(MI.getNumOperands() == 3 &&
|
|
MI.getOperand(0).isRegister() &&
|
|
MI.getOperand(1).isRegister() &&
|
|
MI.getOperand(2).isRegister() &&
|
|
"invalid PPC OR instruction!");
|
|
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
|
|
sourceReg = MI.getOperand(1).getReg();
|
|
destReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
}
|
|
} else if (oc == PPC::ADDI) { // addi r1, r2, 0
|
|
assert(MI.getNumOperands() == 3 &&
|
|
MI.getOperand(0).isRegister() &&
|
|
MI.getOperand(2).isImmediate() &&
|
|
"invalid PPC ADDI instruction!");
|
|
if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
|
|
sourceReg = MI.getOperand(1).getReg();
|
|
destReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
}
|
|
} else if (oc == PPC::ORI) { // ori r1, r2, 0
|
|
assert(MI.getNumOperands() == 3 &&
|
|
MI.getOperand(0).isRegister() &&
|
|
MI.getOperand(1).isRegister() &&
|
|
MI.getOperand(2).isImmediate() &&
|
|
"invalid PPC ORI instruction!");
|
|
if (MI.getOperand(2).getImmedValue()==0) {
|
|
sourceReg = MI.getOperand(1).getReg();
|
|
destReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
}
|
|
} else if (oc == PPC::FMR) { // fmr r1, r2
|
|
assert(MI.getNumOperands() == 2 &&
|
|
MI.getOperand(0).isRegister() &&
|
|
MI.getOperand(1).isRegister() &&
|
|
"invalid PPC FMR instruction");
|
|
sourceReg = MI.getOperand(1).getReg();
|
|
destReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
|
|
assert(MI.getNumOperands() == 2 &&
|
|
MI.getOperand(0).isRegister() &&
|
|
MI.getOperand(1).isRegister() &&
|
|
"invalid PPC MCRF instruction");
|
|
sourceReg = MI.getOperand(1).getReg();
|
|
destReg = MI.getOperand(0).getReg();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|