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Use the new instruction deprecation feature to mark mftb (now replaced with mfspr) and dst (along with the other Altivec cache control instructions) as deprecated when targeting cores supporting at least ISA v2.03. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
220 lines
7.0 KiB
C++
220 lines
7.0 KiB
C++
//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCSubtarget.h"
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cstdlib>
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "PPCGenSubtargetInfo.inc"
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using namespace llvm;
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PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool is64Bit)
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: PPCGenSubtargetInfo(TT, CPU, FS)
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, IsPPC64(is64Bit)
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, TargetTriple(TT) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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/// SetJITMode - This is called to inform the subtarget info that we are
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/// producing code for the JIT.
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void PPCSubtarget::SetJITMode() {
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// JIT mode doesn't want lazy resolver stubs, it knows exactly where
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// everything is. This matters for PPC64, which codegens in PIC mode without
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// stubs.
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HasLazyResolverStubs = false;
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// Calls to external functions need to use indirect calls
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IsJITCodeModel = true;
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}
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void PPCSubtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-cpu");
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Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-features");
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std::string CPU =
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!CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : "";
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std::string FS =
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!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
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if (!FS.empty()) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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}
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void PPCSubtarget::initializeEnvironment() {
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StackAlignment = 16;
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DarwinDirective = PPC::DIR_NONE;
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HasMFOCRF = false;
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Has64BitSupport = false;
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Use64BitRegs = false;
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HasAltivec = false;
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HasQPX = false;
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HasFCPSGN = false;
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HasFSQRT = false;
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HasFRE = false;
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HasFRES = false;
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HasFRSQRTE = false;
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HasFRSQRTES = false;
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HasRecipPrec = false;
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HasSTFIWX = false;
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HasLFIWAX = false;
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HasFPRND = false;
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HasFPCVT = false;
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HasISEL = false;
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HasPOPCNTD = false;
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HasLDBRX = false;
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IsBookE = false;
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DeprecatedMFTB = false;
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DeprecatedDST = false;
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HasLazyResolverStubs = false;
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IsJITCodeModel = false;
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}
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void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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#if (defined(__APPLE__) || defined(__linux__)) && \
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(defined(__ppc__) || defined(__powerpc__))
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if (CPUName == "generic")
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CPUName = sys::getHostCPUName();
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#endif
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Make sure 64-bit features are available when CPUname is generic
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std::string FullFS = FS;
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// If we are generating code for ppc64, verify that options make sense.
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if (IsPPC64) {
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Has64BitSupport = true;
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// Silently force 64-bit register use on ppc64.
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Use64BitRegs = true;
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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}
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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// If the user requested use of 64-bit regs, but the cpu selected doesn't
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// support it, ignore.
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if (use64BitRegs() && !has64BitSupport())
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Use64BitRegs = false;
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// Set up darwin-specific properties.
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if (isDarwin())
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HasLazyResolverStubs = true;
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// QPX requires a 32-byte aligned stack. Note that we need to do this if
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// we're compiling for a BG/Q system regardless of whether or not QPX
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// is enabled because external functions will assume this alignment.
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if (hasQPX() || isBGQ())
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StackAlignment = 32;
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// Determine endianness.
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IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
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}
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/// hasLazyResolverStub - Return true if accesses to the specified global have
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/// to go through a dyld lazy resolution stub. This means that an extra load
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/// is required to get the address of the global.
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bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// We never have stubs if HasLazyResolverStubs=false or if in static mode.
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if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
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return false;
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// If symbol visibility is hidden, the extra load is not needed if
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// the symbol is definitely defined in the current translation unit.
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bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
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if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
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return false;
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return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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GV->hasCommonLinkage() || isDecl;
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}
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bool PPCSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtargetInfo::ANTIDEP_ALL;
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CriticalPathRCs.clear();
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if (isPPC64())
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CriticalPathRCs.push_back(&PPC::G8RCRegClass);
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else
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CriticalPathRCs.push_back(&PPC::GPRCRegClass);
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return OptLevel >= CodeGenOpt::Default;
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}
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// Embedded cores need aggressive scheduling.
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static bool needsAggressiveScheduling(unsigned Directive) {
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switch (Directive) {
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default: return false;
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case PPC::DIR_440:
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case PPC::DIR_A2:
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case PPC::DIR_E500mc:
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case PPC::DIR_E5500:
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return true;
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}
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}
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bool PPCSubtarget::enableMachineScheduler() const {
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// Enable MI scheduling for the embedded cores.
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// FIXME: Enable this for all cores (some additional modeling
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// may be necessary).
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return needsAggressiveScheduling(DarwinDirective);
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}
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void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin,
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MachineInstr *end,
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unsigned NumRegionInstrs) const {
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if (needsAggressiveScheduling(DarwinDirective)) {
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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}
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// Spilling is generally expensive on all PPC cores, so always enable
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// register-pressure tracking.
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Policy.ShouldTrackPressure = true;
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}
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bool PPCSubtarget::useAA() const {
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// Use AA during code generation for the embedded cores.
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return needsAggressiveScheduling(DarwinDirective);
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}
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