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The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
405 lines
13 KiB
C++
405 lines
13 KiB
C++
//===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass implements instructions packetization for R600. It unsets isLast
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/// bit of instructions inside a bundle and substitutes src register with
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/// PreviousVector when applicable.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "packets"
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#include "llvm/Support/Debug.h"
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#include "AMDGPU.h"
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#include "R600InstrInfo.h"
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class R600Packetizer : public MachineFunctionPass {
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public:
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static char ID;
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R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const {
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return "R600 Packetizer";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char R600Packetizer::ID = 0;
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class R600PacketizerList : public VLIWPacketizerList {
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private:
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const R600InstrInfo *TII;
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const R600RegisterInfo &TRI;
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bool VLIW5;
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bool ConsideredInstUsesAlreadyWrittenVectorElement;
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unsigned getSlot(const MachineInstr *MI) const {
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return TRI.getHWRegChan(MI->getOperand(0).getReg());
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}
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/// \returns register to PV chan mapping for bundle/single instructions that
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/// immediatly precedes I.
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DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
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const {
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DenseMap<unsigned, unsigned> Result;
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I--;
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if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
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return Result;
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MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
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if (I->isBundle())
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BI++;
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int LastDstChan = -1;
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do {
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bool isTrans = false;
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int BISlot = getSlot(BI);
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if (LastDstChan >= BISlot)
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isTrans = true;
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LastDstChan = BISlot;
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if (TII->isPredicated(BI))
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continue;
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int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
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if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
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continue;
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int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
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if (DstIdx == -1) {
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continue;
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}
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unsigned Dst = BI->getOperand(DstIdx).getReg();
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if (isTrans || TII->isTransOnly(BI)) {
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Result[Dst] = AMDGPU::PS;
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continue;
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}
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if (BI->getOpcode() == AMDGPU::DOT4_r600 ||
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BI->getOpcode() == AMDGPU::DOT4_eg) {
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Result[Dst] = AMDGPU::PV_X;
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continue;
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}
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if (Dst == AMDGPU::OQAP) {
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continue;
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}
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unsigned PVReg = 0;
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switch (TRI.getHWRegChan(Dst)) {
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case 0:
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PVReg = AMDGPU::PV_X;
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break;
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case 1:
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PVReg = AMDGPU::PV_Y;
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break;
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case 2:
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PVReg = AMDGPU::PV_Z;
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break;
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case 3:
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PVReg = AMDGPU::PV_W;
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break;
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default:
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llvm_unreachable("Invalid Chan");
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}
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Result[Dst] = PVReg;
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} while ((++BI)->isBundledWithPred());
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return Result;
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}
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void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs)
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const {
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unsigned Ops[] = {
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AMDGPU::OpName::src0,
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AMDGPU::OpName::src1,
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AMDGPU::OpName::src2
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};
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for (unsigned i = 0; i < 3; i++) {
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int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]);
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if (OperandIdx < 0)
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continue;
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unsigned Src = MI->getOperand(OperandIdx).getReg();
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const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
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if (It != PVs.end())
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MI->getOperand(OperandIdx).setReg(It->second);
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}
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}
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public:
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// Ctor.
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R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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MachineDominatorTree &MDT)
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: VLIWPacketizerList(MF, MLI, MDT, true),
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TII (static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo())),
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TRI(TII->getRegisterInfo()) {
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VLIW5 = !MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
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}
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// initPacketizerState - initialize some internal flags.
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void initPacketizerState() {
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ConsideredInstUsesAlreadyWrittenVectorElement = false;
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}
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// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB) {
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return false;
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}
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// isSoloInstruction - return true if instruction MI can not be packetized
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// with any other instruction, which means that MI itself is a packet.
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bool isSoloInstruction(MachineInstr *MI) {
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if (TII->isVector(*MI))
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return true;
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if (!TII->isALUInstr(MI->getOpcode()))
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return true;
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if (MI->getOpcode() == AMDGPU::GROUP_BARRIER)
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return true;
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// XXX: This can be removed once the packetizer properly handles all the
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// LDS instruction group restrictions.
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if (TII->isLDSInstr(MI->getOpcode()))
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return true;
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return false;
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}
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// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
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// together.
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bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
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if (getSlot(MII) == getSlot(MIJ))
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ConsideredInstUsesAlreadyWrittenVectorElement = true;
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// Does MII and MIJ share the same pred_sel ?
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int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
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OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
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unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
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PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg():0;
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if (PredI != PredJ)
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return false;
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if (SUJ->isSucc(SUI)) {
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for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
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const SDep &Dep = SUJ->Succs[i];
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if (Dep.getSUnit() != SUI)
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continue;
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if (Dep.getKind() == SDep::Anti)
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continue;
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if (Dep.getKind() == SDep::Output)
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if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
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continue;
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return false;
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}
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}
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bool ARDef = TII->definesAddressRegister(MII) ||
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TII->definesAddressRegister(MIJ);
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bool ARUse = TII->usesAddressRegister(MII) ||
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TII->usesAddressRegister(MIJ);
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if (ARDef && ARUse)
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return false;
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return true;
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}
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// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
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// and SUJ.
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bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {return false;}
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void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
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unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
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MI->getOperand(LastOp).setImm(Bit);
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}
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bool isBundlableWithCurrentPMI(MachineInstr *MI,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<R600InstrInfo::BankSwizzle> &BS,
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bool &isTransSlot) {
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isTransSlot = TII->isTransOnly(MI);
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assert (!isTransSlot || VLIW5);
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// Is the dst reg sequence legal ?
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if (!isTransSlot && !CurrentPacketMIs.empty()) {
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if (getSlot(MI) <= getSlot(CurrentPacketMIs.back())) {
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if (ConsideredInstUsesAlreadyWrittenVectorElement &&
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!TII->isVectorOnly(MI) && VLIW5) {
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isTransSlot = true;
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DEBUG(dbgs() << "Considering as Trans Inst :"; MI->dump(););
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}
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else
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return false;
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}
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}
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// Are the Constants limitations met ?
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CurrentPacketMIs.push_back(MI);
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if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
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DEBUG(
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dbgs() << "Couldn't pack :\n";
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MI->dump();
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dbgs() << "with the following packets :\n";
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for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
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CurrentPacketMIs[i]->dump();
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dbgs() << "\n";
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}
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dbgs() << "because of Consts read limitations\n";
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);
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CurrentPacketMIs.pop_back();
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return false;
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}
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// Is there a BankSwizzle set that meet Read Port limitations ?
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if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
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PV, BS, isTransSlot)) {
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DEBUG(
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dbgs() << "Couldn't pack :\n";
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MI->dump();
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dbgs() << "with the following packets :\n";
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for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
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CurrentPacketMIs[i]->dump();
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dbgs() << "\n";
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}
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dbgs() << "because of Read port limitations\n";
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);
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CurrentPacketMIs.pop_back();
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return false;
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}
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// We cannot read LDS source registrs from the Trans slot.
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if (isTransSlot && TII->readsLDSSrcReg(MI))
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return false;
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CurrentPacketMIs.pop_back();
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return true;
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}
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MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
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MachineBasicBlock::iterator FirstInBundle =
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CurrentPacketMIs.empty() ? MI : CurrentPacketMIs.front();
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const DenseMap<unsigned, unsigned> &PV =
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getPreviousVector(FirstInBundle);
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std::vector<R600InstrInfo::BankSwizzle> BS;
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bool isTransSlot;
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if (isBundlableWithCurrentPMI(MI, PV, BS, isTransSlot)) {
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for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
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MachineInstr *MI = CurrentPacketMIs[i];
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unsigned Op = TII->getOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::bank_swizzle);
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MI->getOperand(Op).setImm(BS[i]);
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}
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unsigned Op = TII->getOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::bank_swizzle);
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MI->getOperand(Op).setImm(BS.back());
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if (!CurrentPacketMIs.empty())
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setIsLastBit(CurrentPacketMIs.back(), 0);
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substitutePV(MI, PV);
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MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
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if (isTransSlot) {
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endPacket(llvm::next(It)->getParent(), llvm::next(It));
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}
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return It;
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}
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endPacket(MI->getParent(), MI);
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if (TII->isTransOnly(MI))
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return MI;
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return VLIWPacketizerList::addToPacket(MI);
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}
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};
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bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
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const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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// Instantiate the packetizer.
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R600PacketizerList Packetizer(Fn, MLI, MDT);
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// DFA state table should not be empty.
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assert(Packetizer.getResourceTracker() && "Empty DFA table!");
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//
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// Loop over all basic blocks and remove KILL pseudo-instructions
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// These instructions confuse the dependence analysis. Consider:
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// D0 = ... (Insn 0)
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// R0 = KILL R0, D0 (Insn 1)
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// R0 = ... (Insn 2)
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// Here, Insn 1 will result in the dependence graph not emitting an output
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// dependence between Insn 0 and Insn 2. This can lead to incorrect
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// packetization
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//
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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MachineBasicBlock::iterator End = MBB->end();
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MachineBasicBlock::iterator MI = MBB->begin();
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while (MI != End) {
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if (MI->isKill() || MI->getOpcode() == AMDGPU::IMPLICIT_DEF ||
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(MI->getOpcode() == AMDGPU::CF_ALU && !MI->getOperand(8).getImm())) {
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MachineBasicBlock::iterator DeleteMI = MI;
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++MI;
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MBB->erase(DeleteMI);
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End = MBB->end();
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continue;
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}
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++MI;
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}
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}
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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// Find scheduling regions and schedule / packetize each region.
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unsigned RemainingCount = MBB->size();
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for(MachineBasicBlock::iterator RegionEnd = MBB->end();
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RegionEnd != MBB->begin();) {
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// The next region starts above the previous region. Look backward in the
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// instruction stream until we find the nearest boundary.
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MachineBasicBlock::iterator I = RegionEnd;
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for(;I != MBB->begin(); --I, --RemainingCount) {
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if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
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break;
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}
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I = MBB->begin();
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// Skip empty scheduling regions.
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if (I == RegionEnd) {
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RegionEnd = llvm::prior(RegionEnd);
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--RemainingCount;
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continue;
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}
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// Skip regions with one instruction.
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if (I == llvm::prior(RegionEnd)) {
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RegionEnd = llvm::prior(RegionEnd);
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continue;
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}
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Packetizer.PacketizeMIs(MBB, I, RegionEnd);
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RegionEnd = I;
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}
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}
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return true;
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}
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} // end anonymous namespace
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llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
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return new R600Packetizer(tm);
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}
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