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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.5 KiB
LLVM
49 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
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; Tests for indirect addressing on SI, which is implemented using dynamic
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; indexing of vectors.
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; CHECK: extract_w_offset
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = add i32 %in, 1
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%1 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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; CHECK: extract_wo_offset
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in
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store float %0, float addrspace(1)* %out
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ret void
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}
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; CHECK: insert_w_offset
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movreld_b32_e32
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define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = add i32 %in, 1
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%1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
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%2 = extractelement <4 x float> %1, i32 2
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store float %2, float addrspace(1)* %out
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ret void
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}
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; CHECK: insert_wo_offset
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movreld_b32_e32
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define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
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%1 = extractelement <4 x float> %0, i32 2
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store float %1, float addrspace(1)* %out
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ret void
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}
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