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23306deb92
For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.7 KiB
TableGen
47 lines
1.7 KiB
TableGen
//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel TSX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TSX instructions
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def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
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[SDNPHasChain, SDNPSideEffect]>;
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let usesCustomInserter = 1 in
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def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
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"# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
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Requires<[HasRTM]>;
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let isBranch = 1, isTerminator = 1, Defs = [EAX] in
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def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
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"xbegin\t$dst", []>, Requires<[HasRTM]>;
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def XEND : I<0x01, MRM_D5, (outs), (ins),
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"xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
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let Defs = [EFLAGS] in
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def XTEST : I<0x01, MRM_D6, (outs), (ins),
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"xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
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def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
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"xabort\t$imm",
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[(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
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// HLE prefixes
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def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>;
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def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>;
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