mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d7c2c86239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28790 91177308-0d34-0410-b5e6-96231b3b80d8
466 lines
17 KiB
C++
466 lines
17 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wrap target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes throw exceptions on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenIntrinsics.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include <set>
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#include <algorithm>
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using namespace llvm;
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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/// getValueType - Return the MCV::ValueType that the specified TableGen record
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/// corresponds to.
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MVT::ValueType llvm::getValueType(Record *Rec, const CodeGenTarget *CGT) {
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return (MVT::ValueType)Rec->getValueAsInt("Value");
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}
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std::string llvm::getName(MVT::ValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::void";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::iPTR: return "TLI.getPointerTy()";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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std::string llvm::getEnumName(MVT::ValueType T) {
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switch (T) {
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case MVT::Other: return "MVT::Other";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::isVoid";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::iPTR: return "TLI.getPointerTy()";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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std::ostream &llvm::operator<<(std::ostream &OS, MVT::ValueType T) {
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return OS << getName(T);
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget() {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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throw std::string("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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throw std::string("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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}
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const std::string &CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
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return LI[AsmWriterNum];
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}
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void CodeGenTarget::ReadRegisters() const {
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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if (Regs.empty())
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throw std::string("No 'Register' subclasses defined!");
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Registers.reserve(Regs.size());
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Registers.assign(Regs.begin(), Regs.end());
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}
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CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
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DeclaredSpillSize = R->getValueAsInt("SpillSize");
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DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadRegisterClasses() const {
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std::vector<Record*> RegClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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if (RegClasses.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegisterClasses.reserve(RegClasses.size());
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RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
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}
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std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
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std::vector<unsigned char> Result;
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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if (R == RC.Elements[ei]) {
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const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes();
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for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
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Result.push_back(InVTs[i]);
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}
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}
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}
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return Result;
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}
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CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
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for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
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Record *Type = TypeList[i];
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if (!Type->isSubClassOf("ValueType"))
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throw "RegTypes list member '" + Type->getName() +
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"' does not derive from the ValueType class!";
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VTs.push_back(getValueType(Type));
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
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for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
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Record *Reg = RegList[i];
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if (!Reg->isSubClassOf("Register"))
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throw "Register Class member '" + Reg->getName() +
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"' does not derive from the Register class!";
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Elements.push_back(Reg);
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}
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// Allow targets to override the size in bits of the RegisterClass.
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unsigned Size = R->getValueAsInt("Size");
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Namespace = R->getValueAsString("Namespace");
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SpillSize = Size ? Size : MVT::getSizeInBits(VTs[0]);
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SpillAlignment = R->getValueAsInt("Alignment");
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MethodBodies = R->getValueAsCode("MethodBodies");
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MethodProtos = R->getValueAsCode("MethodProtos");
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}
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const std::string &CodeGenRegisterClass::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i)
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for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
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LegalValueTypes.push_back(RCs[i].VTs[ri]);
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// Remove duplicates.
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std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
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LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
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LegalValueTypes.end()),
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LegalValueTypes.end());
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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throw std::string("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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std::string InstFormatName =
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getAsmWriter()->getValueAsString("InstFormatName");
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for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
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std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
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Instructions.insert(std::make_pair(Insts[i]->getName(),
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CodeGenInstruction(Insts[i], AsmStr)));
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}
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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void CodeGenTarget::
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getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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&NumberedInstructions) {
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std::map<std::string, CodeGenInstruction>::const_iterator I;
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I = getInstructions().find("PHI");
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if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
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const CodeGenInstruction *PHI = &I->second;
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I = getInstructions().find("INLINEASM");
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if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
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const CodeGenInstruction *INLINEASM = &I->second;
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// Print out the rest of the instructions now.
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NumberedInstructions.push_back(PHI);
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NumberedInstructions.push_back(INLINEASM);
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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if (&II->second != PHI &&&II->second != INLINEASM)
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NumberedInstructions.push_back(&II->second);
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
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: TheDef(R), AsmString(AsmStr) {
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Name = R->getValueAsString("Name");
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Namespace = R->getValueAsString("Namespace");
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isReturn = R->getValueAsBit("isReturn");
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isBranch = R->getValueAsBit("isBranch");
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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isLoad = R->getValueAsBit("isLoad");
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isStore = R->getValueAsBit("isStore");
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isTwoAddress = R->getValueAsBit("isTwoAddress");
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isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
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isCommutable = R->getValueAsBit("isCommutable");
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isTerminator = R->getValueAsBit("isTerminator");
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hasDelaySlot = R->getValueAsBit("hasDelaySlot");
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usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
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hasCtrlDep = R->getValueAsBit("hasCtrlDep");
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noResults = R->getValueAsBit("noResults");
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hasVariableNumberOfOperands = false;
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DagInit *DI;
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try {
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DI = R->getValueAsDag("OperandList");
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} catch (...) {
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// Error getting operand list, just ignore it (sparcv9).
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AsmString.clear();
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OperandList.clear();
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return;
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}
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unsigned MIOperandNo = 0;
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std::set<std::string> OperandNames;
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for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
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DefInit *Arg = dynamic_cast<DefInit*>(DI->getArg(i));
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if (!Arg)
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throw "Illegal operand for the '" + R->getName() + "' instruction!";
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Record *Rec = Arg->getDef();
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std::string PrintMethod = "printOperand";
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unsigned NumOps = 1;
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DagInit *MIOpInfo = 0;
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if (Rec->isSubClassOf("Operand")) {
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PrintMethod = Rec->getValueAsString("PrintMethod");
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NumOps = Rec->getValueAsInt("NumMIOperands");
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MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
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} else if (Rec->getName() == "variable_ops") {
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hasVariableNumberOfOperands = true;
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continue;
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} else if (!Rec->isSubClassOf("RegisterClass"))
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throw "Unknown operand class '" + Rec->getName() +
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"' in instruction '" + R->getName() + "' instruction!";
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// Check that the operand has a name and that it's unique.
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if (DI->getArgName(i).empty())
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throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
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" has no name!";
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if (!OperandNames.insert(DI->getArgName(i)).second)
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throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
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" has the same name as a previous operand!";
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OperandList.push_back(OperandInfo(Rec, DI->getArgName(i), PrintMethod,
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MIOperandNo, NumOps, MIOpInfo));
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MIOperandNo += NumOps;
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}
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}
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/// getOperandNamed - Return the index of the operand with the specified
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/// non-empty name. If the instruction does not have an operand with the
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/// specified name, throw an exception.
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///
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unsigned CodeGenInstruction::getOperandNamed(const std::string &Name) const {
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assert(!Name.empty() && "Cannot search for operand with no name!");
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for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
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if (OperandList[i].Name == Name) return i;
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throw "Instruction '" + TheDef->getName() +
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"' does not have an operand named '$" + Name + "'!";
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}
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//===----------------------------------------------------------------------===//
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// ComplexPattern implementation
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//
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ComplexPattern::ComplexPattern(Record *R) {
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Ty = ::getValueType(R->getValueAsDef("Ty"));
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NumOperands = R->getValueAsInt("NumOperands");
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SelectFunc = R->getValueAsString("SelectFunc");
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RootNodes = R->getValueAsListOfDefs("RootNodes");
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}
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//===----------------------------------------------------------------------===//
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// CodeGenIntrinsic Implementation
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//===----------------------------------------------------------------------===//
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std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC) {
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std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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std::vector<CodeGenIntrinsic> Result;
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// If we are in the context of a target .td file, get the target info so that
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// we can decode the current intptr_t.
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CodeGenTarget *CGT = 0;
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if (Records.getClass("Target") &&
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Records.getAllDerivedDefinitions("Target").size() == 1)
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CGT = new CodeGenTarget();
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for (unsigned i = 0, e = I.size(); i != e; ++i)
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Result.push_back(CodeGenIntrinsic(I[i], CGT));
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delete CGT;
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return Result;
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}
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CodeGenIntrinsic::CodeGenIntrinsic(Record *R, CodeGenTarget *CGT) {
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TheDef = R;
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std::string DefName = R->getName();
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ModRef = WriteMem;
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if (DefName.size() <= 4 ||
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std::string(DefName.begin(), DefName.begin()+4) != "int_")
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throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
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EnumName = std::string(DefName.begin()+4, DefName.end());
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if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
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GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
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TargetPrefix = R->getValueAsString("TargetPrefix");
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Name = R->getValueAsString("LLVMName");
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if (Name == "") {
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// If an explicit name isn't specified, derive one from the DefName.
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Name = "llvm.";
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for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
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if (EnumName[i] == '_')
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Name += '.';
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else
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Name += EnumName[i];
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} else {
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// Verify it starts with "llvm.".
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if (Name.size() <= 5 ||
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std::string(Name.begin(), Name.begin()+5) != "llvm.")
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throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
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}
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// If TargetPrefix is specified, make sure that Name starts with
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// "llvm.<targetprefix>.".
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if (!TargetPrefix.empty()) {
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if (Name.size() < 6+TargetPrefix.size() ||
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std::string(Name.begin()+5, Name.begin()+6+TargetPrefix.size())
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!= (TargetPrefix+"."))
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throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
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TargetPrefix + ".'!";
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}
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// Parse the list of argument types.
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ListInit *TypeList = R->getValueAsListInit("Types");
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for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
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DefInit *DI = dynamic_cast<DefInit*>(TypeList->getElement(i));
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assert(DI && "Invalid list type!");
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Record *TyEl = DI->getDef();
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assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
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ArgTypes.push_back(TyEl->getValueAsString("TypeVal"));
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if (CGT)
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ArgVTs.push_back(getValueType(TyEl->getValueAsDef("VT"), CGT));
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ArgTypeDefs.push_back(TyEl);
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}
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if (ArgTypes.size() == 0)
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throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!";
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// Parse the intrinsic properties.
|
|
ListInit *PropList = R->getValueAsListInit("Properties");
|
|
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
|
|
DefInit *DI = dynamic_cast<DefInit*>(PropList->getElement(i));
|
|
assert(DI && "Invalid list type!");
|
|
Record *Property = DI->getDef();
|
|
assert(Property->isSubClassOf("IntrinsicProperty") &&
|
|
"Expected a property!");
|
|
|
|
if (Property->getName() == "IntrNoMem")
|
|
ModRef = NoMem;
|
|
else if (Property->getName() == "IntrReadArgMem")
|
|
ModRef = ReadArgMem;
|
|
else if (Property->getName() == "IntrReadMem")
|
|
ModRef = ReadMem;
|
|
else if (Property->getName() == "IntrWriteArgMem")
|
|
ModRef = WriteArgMem;
|
|
else if (Property->getName() == "IntrWriteMem")
|
|
ModRef = WriteMem;
|
|
else
|
|
assert(0 && "Unknown property!");
|
|
}
|
|
}
|