mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
488 lines
19 KiB
C++
488 lines
19 KiB
C++
//===-- LegalizeTypesPromote.cpp - Promotion for LegalizeTypes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements promotion support for LegalizeTypes. Promotion is the
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// act of changing a computation in an invalid type to be a computation in a
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// larger type. For example, implementing i8 arithmetic in an i32 register (as
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// is often needed on powerpc for example).
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//
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Result Promotion
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//===----------------------------------------------------------------------===//
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/// PromoteResult - This method is called when a result of a node is found to be
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/// in need of promotion to a larger type. At this point, the node may also
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/// have invalid operands or may have other results that need expansion, we just
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/// know that (at least) one result needs promotion.
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void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
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DEBUG(cerr << "Promote node result: "; N->dump(&DAG); cerr << "\n");
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SDOperand Result = SDOperand();
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "PromoteResult #" << ResNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to promote this operator!");
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abort();
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case ISD::UNDEF: Result = PromoteResult_UNDEF(N); break;
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case ISD::Constant: Result = PromoteResult_Constant(N); break;
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case ISD::TRUNCATE: Result = PromoteResult_TRUNCATE(N); break;
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND: Result = PromoteResult_INT_EXTEND(N); break;
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case ISD::FP_ROUND: Result = PromoteResult_FP_ROUND(N); break;
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
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case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
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case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
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case ISD::SDIV:
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case ISD::SREM: Result = PromoteResult_SDIV(N); break;
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case ISD::UDIV:
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case ISD::UREM: Result = PromoteResult_UDIV(N); break;
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case ISD::SHL: Result = PromoteResult_SHL(N); break;
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case ISD::SRA: Result = PromoteResult_SRA(N); break;
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case ISD::SRL: Result = PromoteResult_SRL(N); break;
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case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
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case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
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}
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// If Result is null, the sub-method took care of registering the result.
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if (Result.Val)
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SetPromotedOp(SDOperand(N, ResNo), Result);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
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return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
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MVT::ValueType VT = N->getValueType(0);
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// Zero extend things like i1, sign extend everything else. It shouldn't
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// matter in theory which one we pick, but this tends to give better code?
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unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
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SDOperand(N, 0));
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assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
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return Result;
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}
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SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
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SDOperand Res;
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switch (getTypeAction(N->getOperand(0).getValueType())) {
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default: assert(0 && "Unknown type action!");
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case Legal:
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case Expand:
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Res = N->getOperand(0);
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break;
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case Promote:
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Res = GetPromotedOp(N->getOperand(0));
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break;
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}
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MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
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"Truncation doesn't make sense!");
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if (Res.getValueType() == NVT)
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return Res;
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// Truncate to NVT instead of VT
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return DAG.getNode(ISD::TRUNCATE, NVT, Res);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
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MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
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SDOperand Res = GetPromotedOp(N->getOperand(0));
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assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
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"Extension doesn't make sense!");
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// If the result and operand types are the same after promotion, simplify
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// to an in-register extension.
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if (NVT == Res.getValueType()) {
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// The high bits are not guaranteed to be anything. Insert an extend.
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if (N->getOpcode() == ISD::SIGN_EXTEND)
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
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DAG.getValueType(N->getOperand(0).getValueType()));
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if (N->getOpcode() == ISD::ZERO_EXTEND)
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return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
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assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
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return Res;
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}
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}
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// Otherwise, just extend the original operand all the way to the larger type.
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return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
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// NOTE: Assumes input is legal.
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return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
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N->getOperand(0), DAG.getValueType(N->getValueType(0)));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
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SDOperand Op = N->getOperand(0);
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// If the operand needed to be promoted, do so now.
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if (getTypeAction(Op.getValueType()) == Promote)
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// The input result is prerounded, so we don't have to do anything special.
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Op = GetPromotedOp(Op);
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unsigned NewOpc = N->getOpcode();
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MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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// If we're promoting a UINT to a larger size, check to see if the new node
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// will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
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// we can use that instead. This allows us to generate better code for
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// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
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// legal, such as PowerPC.
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if (N->getOpcode() == ISD::FP_TO_UINT) {
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if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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(TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
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TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
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NewOpc = ISD::FP_TO_SINT;
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}
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return DAG.getNode(NewOpc, NVT, Op);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
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assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
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return DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), N->getOperand(0),
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N->getOperand(1), N->getOperand(2));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
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MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
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ISD::LoadExtType ExtType =
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ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
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SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
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N->getSrcValue(), N->getSrcValueOffset(),
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N->getLoadedVT(), N->isVolatile(),
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N->getAlignment());
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
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return Res;
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
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// The input may have strange things in the top bits of the registers, but
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// these operations don't care. They may have weird bits going out, but
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// that too is okay if they are integer operations.
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SDOperand LHS = GetPromotedOp(N->getOperand(0));
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SDOperand RHS = GetPromotedOp(N->getOperand(1));
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return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
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// Sign extend the input.
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SDOperand LHS = GetPromotedOp(N->getOperand(0));
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SDOperand RHS = GetPromotedOp(N->getOperand(1));
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MVT::ValueType VT = N->getValueType(0);
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LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
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DAG.getValueType(VT));
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RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
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DAG.getValueType(VT));
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return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
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// Zero extend the input.
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SDOperand LHS = GetPromotedOp(N->getOperand(0));
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SDOperand RHS = GetPromotedOp(N->getOperand(1));
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MVT::ValueType VT = N->getValueType(0);
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LHS = DAG.getZeroExtendInReg(LHS, VT);
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RHS = DAG.getZeroExtendInReg(RHS, VT);
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return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
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return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
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GetPromotedOp(N->getOperand(0)), N->getOperand(1));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
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// The input value must be properly sign extended.
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
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SDOperand Res = GetPromotedOp(N->getOperand(0));
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Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
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return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
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// The input value must be properly zero extended.
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
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SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
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return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SELECT(SDNode *N) {
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SDOperand LHS = GetPromotedOp(N->getOperand(1));
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SDOperand RHS = GetPromotedOp(N->getOperand(2));
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return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
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}
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SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
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SDOperand LHS = GetPromotedOp(N->getOperand(2));
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SDOperand RHS = GetPromotedOp(N->getOperand(3));
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return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
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N->getOperand(1), LHS, RHS, N->getOperand(4));
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}
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//===----------------------------------------------------------------------===//
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// Operand Promotion
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//===----------------------------------------------------------------------===//
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/// PromoteOperand - This method is called when the specified operand of the
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/// specified node is found to need promotion. At this point, all of the result
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/// types of the node are known to be legal, but other operands of the node may
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/// need promotion or expansion as well as the specified one.
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bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) {
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DEBUG(cerr << "Promote node operand: "; N->dump(&DAG); cerr << "\n");
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SDOperand Res;
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "PromoteOperand Op #" << OpNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to promote this operator's operand!");
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abort();
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case ISD::ANY_EXTEND: Res = PromoteOperand_ANY_EXTEND(N); break;
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case ISD::ZERO_EXTEND: Res = PromoteOperand_ZERO_EXTEND(N); break;
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case ISD::SIGN_EXTEND: Res = PromoteOperand_SIGN_EXTEND(N); break;
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case ISD::TRUNCATE: Res = PromoteOperand_TRUNCATE(N); break;
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case ISD::FP_EXTEND: Res = PromoteOperand_FP_EXTEND(N); break;
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case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
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case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
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case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
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case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
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case ISD::SETCC: Res = PromoteOperand_SETCC(N, OpNo); break;
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case ISD::STORE: Res = PromoteOperand_STORE(cast<StoreSDNode>(N),
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OpNo); break;
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case ISD::MEMSET:
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case ISD::MEMCPY:
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case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
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}
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// If the result is null, the sub-method took care of registering results etc.
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if (!Res.Val) return false;
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// If the result is N, the sub-method updated N in place.
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if (Res.Val == N) {
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// Mark N as new and remark N and its operands. This allows us to correctly
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// revisit N if it needs another step of promotion and allows us to visit
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// any new operands to N.
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N->setNodeId(NewNode);
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MarkNewNodes(N);
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return true;
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}
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assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
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"Invalid operand expansion");
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ReplaceValueWith(SDOperand(N, 0), Res);
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return false;
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_ANY_EXTEND(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_ZERO_EXTEND(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
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return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_SIGN_EXTEND(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
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Op, DAG.getValueType(N->getOperand(0).getValueType()));
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_TRUNCATE(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
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SDOperand Op = GetPromotedOp(N->getOperand(0));
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return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op);
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
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SDOperand In = GetPromotedOp(N->getOperand(0));
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MVT::ValueType OpVT = N->getOperand(0).getValueType();
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if (N->getOpcode() == ISD::UINT_TO_FP)
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In = DAG.getZeroExtendInReg(In, OpVT);
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else
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In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
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In, DAG.getValueType(OpVT));
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return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
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assert(OpNo == 0 && "Only know how to promote condition");
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SDOperand Cond = GetPromotedOp(N->getOperand(0)); // Promote the condition.
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// The top bits of the promoted condition are not necessarily zero, ensure
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// that the value is properly zero extended.
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if (!DAG.MaskedValueIsZero(Cond,
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MVT::getIntVTBitMask(Cond.getValueType())^1)) {
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Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
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MarkNewNodes(Cond.Val);
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}
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// The chain (Op#0) and basic block destination (Op#2) are always legal types.
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return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
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N->getOperand(2));
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}
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SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
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assert(OpNo == 1 && "only know how to promote condition");
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SDOperand Cond = GetPromotedOp(N->getOperand(1)); // Promote the condition.
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// The top bits of the promoted condition are not necessarily zero, ensure
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// that the value is properly zero extended.
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if (!DAG.MaskedValueIsZero(Cond,
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MVT::getIntVTBitMask(Cond.getValueType())^1)) {
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Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
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MarkNewNodes(Cond.Val);
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}
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// The chain (Op#0) and basic block destination (Op#2) are always legal types.
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return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
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N->getOperand(2));
|
|
}
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_BR_CC(SDNode *N, unsigned OpNo) {
|
|
assert(OpNo == 2 && "Don't know how to promote this operand");
|
|
|
|
SDOperand LHS = N->getOperand(2);
|
|
SDOperand RHS = N->getOperand(3);
|
|
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
|
|
|
|
// The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
|
|
// legal types.
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
|
|
N->getOperand(1), LHS, RHS, N->getOperand(4));
|
|
}
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
|
|
assert(OpNo == 0 && "Don't know how to promote this operand");
|
|
|
|
SDOperand LHS = N->getOperand(0);
|
|
SDOperand RHS = N->getOperand(1);
|
|
PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
|
|
|
|
// The CC (#2) is always legal.
|
|
return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
|
|
}
|
|
|
|
/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
|
|
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
|
|
void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
|
|
ISD::CondCode CCCode) {
|
|
MVT::ValueType VT = NewLHS.getValueType();
|
|
|
|
// Get the promoted values.
|
|
NewLHS = GetPromotedOp(NewLHS);
|
|
NewRHS = GetPromotedOp(NewRHS);
|
|
|
|
// If this is an FP compare, the operands have already been extended.
|
|
if (!MVT::isInteger(NewLHS.getValueType()))
|
|
return;
|
|
|
|
// Otherwise, we have to insert explicit sign or zero extends. Note
|
|
// that we could insert sign extends for ALL conditions, but zero extend
|
|
// is cheaper on many machines (an AND instead of two shifts), so prefer
|
|
// it.
|
|
switch (CCCode) {
|
|
default: assert(0 && "Unknown integer comparison!");
|
|
case ISD::SETEQ:
|
|
case ISD::SETNE:
|
|
case ISD::SETUGE:
|
|
case ISD::SETUGT:
|
|
case ISD::SETULE:
|
|
case ISD::SETULT:
|
|
// ALL of these operations will work if we either sign or zero extend
|
|
// the operands (including the unsigned comparisons!). Zero extend is
|
|
// usually a simpler/cheaper operation, so prefer it.
|
|
NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
|
|
NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
|
|
return;
|
|
case ISD::SETGE:
|
|
case ISD::SETGT:
|
|
case ISD::SETLT:
|
|
case ISD::SETLE:
|
|
NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
|
|
DAG.getValueType(VT));
|
|
NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
|
|
DAG.getValueType(VT));
|
|
return;
|
|
}
|
|
}
|
|
|
|
SDOperand DAGTypeLegalizer::PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo){
|
|
SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
|
|
int SVOffset = N->getSrcValueOffset();
|
|
unsigned Alignment = N->getAlignment();
|
|
bool isVolatile = N->isVolatile();
|
|
|
|
SDOperand Val = GetPromotedOp(N->getValue()); // Get promoted value.
|
|
|
|
assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
|
|
|
|
// Truncate the value and store the result.
|
|
return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
|
|
SVOffset, N->getStoredVT(),
|
|
isVolatile, Alignment);
|
|
}
|