mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-26 06:29:20 +00:00
235a81cbbf
IIImul -> II_MUL IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199495 91177308-0d34-0410-b5e6-96231b3b80d8
170 lines
8.5 KiB
TableGen
170 lines
8.5 KiB
TableGen
//===-- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across Mips chips sets. Based on GCC/Mips backend files.
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//===----------------------------------------------------------------------===//
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def ALU : FuncUnit;
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def IMULDIV : FuncUnit;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for Mips
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//===----------------------------------------------------------------------===//
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def IIAlu : InstrItinClass;
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def IILoad : InstrItinClass;
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def IIStore : InstrItinClass;
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def IIBranch : InstrItinClass;
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def IIIdiv : InstrItinClass;
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def IIslt : InstrItinClass;
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def IIFcvt : InstrItinClass;
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def IIFmove : InstrItinClass;
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def IIFcmp : InstrItinClass;
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def IIFadd : InstrItinClass;
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def IIFmulSingle : InstrItinClass;
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def IIFmulDouble : InstrItinClass;
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def IIFdivSingle : InstrItinClass;
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def IIFdivDouble : InstrItinClass;
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def IIFsqrtSingle : InstrItinClass;
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def IIFsqrtDouble : InstrItinClass;
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def IIFrecipFsqrtStep : InstrItinClass;
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def IIFLoad : InstrItinClass;
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def IIFStore : InstrItinClass;
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def IIFmoveC1 : InstrItinClass;
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def IIPseudo : InstrItinClass;
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def II_ADDI : InstrItinClass;
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def II_ADDIU : InstrItinClass;
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def II_ADDU : InstrItinClass;
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def II_AND : InstrItinClass;
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def II_ANDI : InstrItinClass;
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def II_CLO : InstrItinClass;
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def II_CLZ : InstrItinClass;
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def II_DADDIU : InstrItinClass;
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def II_DADDU : InstrItinClass;
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def II_DMULT : InstrItinClass;
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def II_DMULTU : InstrItinClass;
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def II_DROTR : InstrItinClass;
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def II_DROTR32 : InstrItinClass;
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def II_DROTRV : InstrItinClass;
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def II_DSLL : InstrItinClass;
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def II_DSLL32 : InstrItinClass;
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def II_DSLLV : InstrItinClass;
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def II_DSRA : InstrItinClass;
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def II_DSRA32 : InstrItinClass;
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def II_DSRAV : InstrItinClass;
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def II_DSRL : InstrItinClass;
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def II_DSRL32 : InstrItinClass;
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def II_DSRLV : InstrItinClass;
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def II_DSUBU : InstrItinClass;
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def II_LUI : InstrItinClass;
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def II_MADD : InstrItinClass;
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def II_MADDU : InstrItinClass;
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def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
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def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
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def II_MOVF : InstrItinClass;
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def II_MOVN : InstrItinClass;
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def II_MOVT : InstrItinClass;
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def II_MOVZ : InstrItinClass;
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def II_MUL : InstrItinClass;
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def II_MULT : InstrItinClass;
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def II_MULTU : InstrItinClass;
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def II_MSUB : InstrItinClass;
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def II_MSUBU : InstrItinClass;
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def II_NOR : InstrItinClass;
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def II_OR : InstrItinClass;
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def II_ORI : InstrItinClass;
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def II_RDHWR : InstrItinClass;
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def II_ROTR : InstrItinClass;
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def II_ROTRV : InstrItinClass;
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def II_SEB : InstrItinClass;
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def II_SEH : InstrItinClass;
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def II_SLL : InstrItinClass;
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def II_SLLV : InstrItinClass;
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def II_SRA : InstrItinClass;
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def II_SRAV : InstrItinClass;
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def II_SRL : InstrItinClass;
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def II_SRLV : InstrItinClass;
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def II_SUBU : InstrItinClass;
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def II_XOR : InstrItinClass;
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def II_XORI : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Mips Generic instruction itineraries.
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//===----------------------------------------------------------------------===//
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def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SLLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRAV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ROTRV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_CLO , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ANDI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ORI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_XORI , [InstrStage<1, [ALU]>]>,
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InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
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InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>,
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InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
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InstrItinData<IIFcvt , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIFmove , [InstrStage<2, [ALU]>]>,
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InstrItinData<IIFcmp , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIFadd , [InstrStage<4, [ALU]>]>,
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InstrItinData<IIFmulSingle , [InstrStage<7, [ALU]>]>,
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InstrItinData<IIFmulDouble , [InstrStage<8, [ALU]>]>,
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InstrItinData<IIFdivSingle , [InstrStage<23, [ALU]>]>,
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InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
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InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
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InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
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InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>,
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InstrItinData<IIFLoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIFStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIFmoveC1 , [InstrStage<2, [ALU]>]>
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]>;
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