mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2392ae7d73
a load/or/and/store sequence into a narrower store when it is
safe. Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.
This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll
into:
movl %eax, 36(%rdi)
instead of:
movl $4294967295, %eax ## imm = 0xFFFFFFFF
andq 32(%rdi), %rax
shlq $32, %rcx
addq %rax, %rcx
movq %rcx, 32(%rdi)
and each of the testcases into a single store. Each of them used
to compile into craziness like this:
_test4:
movl $65535, %eax ## imm = 0xFFFF
andl (%rdi), %eax
shll $16, %esi
addl %eax, %esi
movl %esi, (%rdi)
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101343 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.1 KiB
LLVM
82 lines
2.1 KiB
LLVM
; rdar://7860110
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.2"
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define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, -256 ; 0xFFFFFF00
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%C = zext i8 %a1 to i32
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%D = or i32 %C, %B
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store i32 %D, i32* %a0, align 4
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ret void
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; CHECK: test1:
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; CHECK: movb %sil, (%rdi)
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}
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define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, -65281 ; 0xFFFF00FF
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%C = zext i8 %a1 to i32
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%CS = shl i32 %C, 8
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%D = or i32 %B, %CS
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store i32 %D, i32* %a0, align 4
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ret void
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; CHECK: test2:
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; CHECK: movb %sil, 1(%rdi)
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}
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define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, -65536 ; 0xFFFF0000
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%C = zext i16 %a1 to i32
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%D = or i32 %B, %C
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store i32 %D, i32* %a0, align 4
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ret void
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; CHECK: test3:
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; CHECK: movw %si, (%rdi)
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}
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define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, 65535 ; 0x0000FFFF
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%C = zext i16 %a1 to i32
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%CS = shl i32 %C, 16
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%D = or i32 %B, %CS
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store i32 %D, i32* %a0, align 4
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ret void
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; CHECK: test4:
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; CHECK: movw %si, 2(%rdi)
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}
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define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
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entry:
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%A = load i64* %a0, align 4
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%B = and i64 %A, -4294901761 ; 0xFFFFFFFF0000FFFF
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%C = zext i16 %a1 to i64
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%CS = shl i64 %C, 16
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%D = or i64 %B, %CS
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store i64 %D, i64* %a0, align 4
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ret void
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; CHECK: test5:
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; CHECK: movw %si, 2(%rdi)
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}
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define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
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entry:
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%A = load i64* %a0, align 4
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%B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF
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%C = zext i8 %a1 to i64
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%CS = shl i64 %C, 40
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%D = or i64 %B, %CS
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store i64 %D, i64* %a0, align 4
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ret void
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; CHECK: test6:
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; CHECK: movb %sil, 5(%rdi)
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}
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