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llvm-6502/lib/Target/ARM
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Chris Lattner 09e460662a Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-05 02:31:13 +00:00
..
.cvsignore
ARM.h
ARM.td
ARMAsmPrinter.cpp
ARMFrameInfo.h
ARMInstrInfo.cpp
ARMInstrInfo.h
ARMInstrInfo.td
ARMISelDAGToDAG.cpp
ARMRegisterInfo.cpp Completely eliminate def&use operands. Now a register operand is EITHER a 2006-09-05 02:31:13 +00:00
ARMRegisterInfo.h
ARMRegisterInfo.td
ARMTargetMachine.cpp
ARMTargetMachine.h
Makefile
README.txt

README.txt 

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b